參數(shù)資料
型號: UPD16682W
廠商: NEC Corp.
英文描述: 1/65 DUTY LCD CONTROLLER/DRIVER WITH ON-CHIP RAM
中文描述: 1 / 65稅LCD控制器/驅動器,片內RAM
文件頁數(shù): 47/56頁
文件大小: 435K
代理商: UPD16682W
Data Sheet S13368EJ3V0DS00
47
μ
PD16682
( V
DD
= 2.4 to 2.7 V )
Parameter
Symbol
Conditions
MIN.
TYP.
Note
MAX.
Unit
Address hold time
t
AH6
A0, R,/W
0
ns
Address setup time
t
AS6
A0, R,/W
0
ns
System cycle time
t
CYC6
1000
ns
Data setup time
t
DS6
D
0
to D
7
80
ns
Data hold time
t
DH6
D
0
to D
7
30
ns
Access time
t
ACC6
D
0
to D
7
, C
L
= 100 pF
280
ns
Output disable time
t
OH6
D
0
to D
7
, C
L
= 100 pF
10
ns
Enable H pulse width
Read
t
EWHR
E
240
ns
Write
t
EWHW
E
120
ns
Enable L pulse width
Read
t
EWLR
E
120
ns
Write
t
EWLW
E
120
ns
Note
The TYP. value is a reference value when T
A
= 25
°
C
Remarks 1.
The rise and fall times (t
r
and t
f
) of input signals are rated at 15 ns or less. When using a fast system
cycle time, the rated value range is either (t
r
+ t
f
)
(t
CYC6
–t
EWLW
–t
EWHW
) or (t
r
+ t
f
)
(t
CYC6
–t
EWLR
–t
EWHR
).
2.
All timing is rated based on 20 % or 80 % of V
DD
.
3.
t
EWHW
and t
EWLW
are rated as the overlap time when /CS1 is at low level (CS2 = H) and E is at high
level.
4.
D
0
to D
7
change to output regardless of the state of the E signal when R,/W becomes H in the state of
/CS1 = L, CS2 = H ( See
5.1.2. (2) 68 Series Parallel Interface.
).
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