參數(shù)資料
型號: UPD16682W
廠商: NEC Corp.
英文描述: 1/65 DUTY LCD CONTROLLER/DRIVER WITH ON-CHIP RAM
中文描述: 1 / 65稅LCD控制器/驅(qū)動(dòng)器,片內(nèi)RAM
文件頁數(shù): 27/56頁
文件大?。?/td> 435K
代理商: UPD16682W
Data Sheet S13368EJ3V0DS00
27
μ
PD16682
12. COMMANDS
The
μ
PD16682 uses a combination of A0, /RD(E), and /WR(R,/W) to identify data bus signals. Command
interpretation and execution is performed using internal timing that does not depend on any external clock.
The 80 series MPU interface activates commands using low pulse input to the /RD pin during read and activates
commands using low pulse input to the /WR pin during write. The 68 series MPU interface sets read mode using
high-level input to the R,/W pin and sets write mode using low-level input to the R,/W pin. The command is activated
using high pulse input to the E pin.
Thus, the 68 series MPU interface differs from the 80 series MPU interface in that /RD(E) is at high level during
status read and display data read operations, as is shown in the command descriptions and command table.
Command descriptions using an 80 series MPU interface are shown below.
If the serial interface has been selected, data is input sequentially starting from D
7
.
12.1 Display ON/OFF
This command specifies the display’s ON/OFF status.
A0
E, /RD
R,/W, /WR
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
Setting
0
1
0
1
0
1
0
1
1
1
1
Display ON
0
Display OFF
Executing the display all ON command while the display is OFF sets power save (low power) mode. For details, see
12.20 Power Save (Compound Command)
.
When the display is OFF, output via all driver outputs (segment and common) is at V
SS
level.
12.2 Display Start Line Set
This command specifies the address of the display start line in the display data RAM, as was shown in Figure 6
2.
The display area extends from the specified line address in the direction of higher line addresses, and includes the
number of lines that corresponds to the display duty setting. The display can be smoothly scrolled vertically by using
this command to dynamically modify the specified line addresses.
For details, see
6.4 Line Address Circuit
.
A0
E, /RD
R,/W, /WR
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
Line Address
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
0
2
1
1
1
1
1
0
62
1
1
1
1
1
1
63
相關(guān)PDF資料
PDF描述
UPD16700 256-OUTPUT TFT-LCD GATE DRIVER
UPD16700N DUSTCAP, METAL SZ22; Material:Zinc Alloy; Colour:Nickel Plated; Connector shell size:22; Voltage rating, AC:750V; Series:TRIM TRIO
UPD16803 MONOLITHIC DUAL H BRIDGE DRIVER CIRCUIT
UPD16803GS MONOLITHIC DUAL H BRIDGE DRIVER CIRCUIT
UPD168103AK9-5B4-A 5-CHANNEL OPERATIONAL AMPLIFIER, IRIS DRIVER, AND 4-CHANNEL H-BRIDGE DRIVER
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
UPD16686 制造商:未知廠家 制造商全稱:未知廠家 功能描述:UPD16686.16687 Data Sheet | Data Sheet[07/2001]
UPD16686P 制造商:NEC 制造商全稱:NEC 功能描述:1/128 DUTY LCD CONTROLLER/DRIVER WITH FOUR-LEVEL GRAY SCALE, ON-CHIP RAM
UPD16686W 制造商:NEC 制造商全稱:NEC 功能描述:1/128 DUTY LCD CONTROLLER/DRIVER WITH FOUR-LEVEL GRAY SCALE, ON-CHIP RAM
UPD16687 制造商:未知廠家 制造商全稱:未知廠家 功能描述:UPD16686.16687 Data Sheet | Data Sheet[07/2001]
UPD16687P 制造商:NEC 制造商全稱:NEC 功能描述:1/128 DUTY LCD CONTROLLER/DRIVER WITH FOUR-LEVEL GRAY SCALE, ON-CHIP RAM