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參數資料
| 型號： | UPD16682W |
| 廠商： | NEC Corp. |
| 英文描述： | 1/65 DUTY LCD CONTROLLER/DRIVER WITH ON-CHIP RAM |
| 中文描述： | 1 / 65稅LCD控制器/驅動器，片內RAM |
| 文件頁數： | 26/56頁 |
| 文件大?。?/td> | 435K |
| 代理商： | UPD16682W |
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Data Sheet S13368EJ3V0DS00
26
μ
PD16682
11. RESET CIRCUIT
In the
μ
PD16682, when the /RES input is at low level, a reset is executed. The reset (default) settings are
described below.
1. Display OFF
2. Normal display direction
3. ADC select: normal direction (ADC command D
0
=L)
4. Power control register: (D
2
,D
1
,D
0
) = (0,0,0)
5. Data cleared from register in serial interface
6. LCD power supply bias: 1/9 bias
7. Read modify write OFF
8. Power save canceled
9. SEG/COM output: V
SS
10.Static indicator OFF
Static indicator register: (D
2
,D
1
) = (0,0)
11.Display start line: set to line 1
12.Column address: set to address 0
13.Page address: set to page 0
14.Common output status: Normal
15.Canceled mode set for on-chip resistance factor for V
LC1
voltage regulator
V
LC1
voltage regulator resistance factor register (D
2
,D
1
,D
0
) = (0,0,0)
16.Canceled mode set for electronic volume register
Electronic volume register: (D
5
,D
4
,D
3
,D
2
,D
1
,D
0
) = (1,0,0,0,0,0)
17.Test mode canceled
18.Display all OFF (display all ON/OFF command, D
0
= L)
Only items 1, 7, and 9 to 18 above are executed when a reset command is used.
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