參數(shù)資料
型號： UPC1854AGT
廠商： NEC Corp.
英文描述： I2C BUS-COMPATIBLE US MTS PROCESSING LSI
中文描述： I2C總線兼容美國的多邊貿(mào)易體制處理LSI
文件頁數(shù)： 18/48頁
文件大?。?/td> 251K
代理商： UPC1854AGT
μ
PC1854A
18
Data Sheet S12816EJ3V0DS00
3. I
2
C BUS INTERFACE
The
μ
PC1854A uses the I
2
C bus interface that is developed by Philips. The serial clock line (SCL) and serial
data line (SDA) employ the 2-wire configuration as shown in
Figure 3-1
.
The
μ
PC1854A contains seven (1 byte 8 bits) write registers and one read register through the I
2
C bus interface
circuit.
Serial Clock Line (SCL)
The master CPU outputs a serial clock to achieve data synchronization. The
μ
PC1854A receives serial data
based on this clock. The input level is CMOS-compatible. The clock frequency is from 0 to 100 kHz.
Serial Data Line (SDA)
The master CPU outputs data synchronously with the serial clock. The
μ
PC1854A receives this data based on
the serial clock. The input level is CMOS-compatible.
Figure 3-1. Internal Equivalent Circuit of Interface Pins
No protection diode is provided on the V
CC
side for the SCL and SDA pins so that the I
2
C bus line is not pulled
to 0 V when the power is OFF (V
CC
= 0 V).
SCL
SDA
R
P
R
P
PC1854A
μ
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