參數(shù)資料
型號： UPC1854AGT
廠商： NEC Corp.
英文描述： I2C BUS-COMPATIBLE US MTS PROCESSING LSI
中文描述： I2C總線兼容美國的多邊貿(mào)易體制處理LSI
文件頁數(shù)： 14/48頁
文件大小： 251K
代理商： UPC1854AGT
μ
PC1854A
14
Data Sheet S12816EJ3V0DS00
2.1 Stereo Demodulation Block
(1) Stereo LPF
This filter eliminates signals in the vicinity of 5 f
H
to 6 f
H
, such as SAP (Sub Audio Program) (5 f
H
) and telemetry
signals (6.5 f
H
) . The
μ
PC1854A’s internal L–R demodulator, which uses a double-balanced circuit, demodu-
lates L–R signals by multiplication of the L–R signal with the signal at the L–R carrier frequency (2 f
H
). The L–
R signal tends to receive interference from the 6 f
H
signal because a square waveform is used as the switching
carrier in this method. To eliminate this interference, the
μ
PC1854A incorporates traps at 5 f
H
and 6 f
H
. The
filter response is adjusted by setting the Filter setting bits (write register, subaddress 02H, bits D0 to D5).
(2) Stereo phase comparator
The 8 f
H
signal generated at the stereo VCO is divided by 8 (4
×
2) and then multiplied by the pilot signal
passed through the stereo LPF. The two signals differ from each other by 90 degrees in terms of phase.
The resistor and capacitor connected to Pins
φ
D1 and
φ
D2 form a filter that smooths the phase error signal
output from the stereo phase comparator, converting the error signal to the DC voltage. When the voltage
difference between pins
φ
D1 and
φ
D2 becomes 0 V (strictly speaking, not 0 V by the internal offset voltage),
the VCO runs at 8 f
H
.
The lag/lead filter externally connected to the pins
φ
D1 and
φ
D2 determines the capture range.
(3) Stereo VCO
The VCO runs at 8 f
H
with the internal capacitor. The frequency is adjusted by setting the Stereo VCO setting
bits (write register, subaddress 01H, bits D0 to D5).
(4) Divider (Flip-flop)
Produces two separate f
H
signals: the inphase f
H
signal, and the f
H
signal differing by 90 degrees from the input
pilot signal by dividing the 8 f
H
frequency from the stereo VCO by 8 (4
×
2).
(5) Pilot discrimination phase comparator (Level detector)
Multiplies the pilot signal from the COM pin with the inphase fH signal from the divider. The resulting signal is
smoothed by passing it through the external filter connected to the PD1 and PD2 pins and converted into DC
voltage value that is used to determine whether or not a stereo pilot signal (read register, bit D6) is present.
(6) Pilot canceler
The f
H
signal from the divider is added to the stereo signal in resistor matrix depending on the level of the input
pilot signal to cancel the pilot signal.
(7) L+R LPF
This LPF which has traps at f
H
and 24 kHz, allows only the monaural signal to pass through. The filter re-
sponse is adjusted by setting the Filter setting bits (write register, subaddress 02H, bits D0 to D5).
(8) De-emphasis
The filter is a 75-
μ
s de-emphasis filter for the monaural signal. The response is adjusted by setting the Filter
setting bits (write register, subaddress 02H, bits D0 to D5).
(9) L–R AM demodulator
Demodulates the L–R AM-DSB modulated signal by multiplying with the 2f
H
signal which is synchronized to the
pilot signal. The 2-f
H
square wave is used as the switching carrier.
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