參數(shù)資料
型號： UPC1830
廠商： NEC Corp.
元件分類： DC/DC變換器
英文描述： RSO-S_D(Z) Series - Econoline Regulated DC-DC Converters; Input Voltage (Vdc): 05V; Output Voltage (Vdc): 15V; Power: 1W; 2:1 and 4:1 Wide Input Voltage Ranges; 1kVDC, 2kVD & 3kVDC Isolation; UL94V-0 Package Material; Continuous Short Circuit Protectionwith Current Foldback; Low Noise; No External Capacitor needed; Efficiency to 83%
中文描述： 過濾含視頻色度，同步信號處理LSI兼容NTSC制式/ PAL制
文件頁數(shù)： 19/44頁
文件大小： 338K
代理商： UPC1830
μ
PC1830
19
Figure 5-7. Sync. Separation Waveform
V
S
in Figure 5-7 represents the slice voltage and can be expressed in the following expression if it is assumed
that C
O
is sufficiently large, and both I
X
and I
SP
are linear.
V
S
= 2.5
×
(R
X
/R
O
)
×
(T2/T1) [V]
The
μ
PC1830 amplifies the part lower than this slice voltage (V
S
) to perform sync. separation.
To determine sync. separation sensitivity, change R
X
to set V
S
. Decreasing V
S
is advantageous for separation
of the horizontal sync. part, but disadvantageous for separation of the vertical sync. part. On the contrary,
increasing V
S
may cause a sync. failure (jitter) due to noise (spikes) of the horizontal sync. part. Therefore, it
is necessary to optimize the constant in accordance with a signal input. As capacitance C
O
, select a sufficiently
large value compared with the charge/discharge current. However, an excessive value may deteriorate the
excessive response characteristic, failing to catch up with drastic APL variations of the input signal.
The larger R
X
, the larger the slice level becomes. However, with large R
X
if the sync. signal level drops (weak
electric field signal, etc.) a video signal may be confused with a sync. signal and sliced, making synchronization
unstable (abnormal).
Caution
Since the measuring circuit uses capacitor coupling for input for ease of measurement, it is
susceptible to APL variations. Therefore, when configuring the actual circuit, use a Sync Tip
clamp circuit in the stage prior to inputting to the emitter follower to stabilize the synchronization
peak potential and this will make the circuit more resistant to APL variations.
(3) Vertical filter circuit
Separates the vertical sync. signal from the sync. signal separated by the sync. separation circuit.
(4) Horizontal sync. detection circuit
Detects the presence of a horizontal sync. signal and changes the AFC time constant.
(5) AFC detection circuit
Performs phase detection on an input sync. signal and f
H
and outputs the phase difference in voltage.
Stops phase detection for 9H of the vertical blanking period.
(6) 32f
H
VCO
Controls VCO according to the voltage output by the AFC detection circuit and generates 32f
H
oscillation clocks.
T1 (4.7 s)
T2 (58.86 s)
Discharge by I
X
Charge by I
SP
V
S
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