參數(shù)資料
型號(hào)： UPC1830
廠商： NEC Corp.
元件分類： DC/DC變換器
英文描述： RSO-S_D(Z) Series - Econoline Regulated DC-DC Converters; Input Voltage (Vdc): 05V; Output Voltage (Vdc): 15V; Power: 1W; 2:1 and 4:1 Wide Input Voltage Ranges; 1kVDC, 2kVD & 3kVDC Isolation; UL94V-0 Package Material; Continuous Short Circuit Protectionwith Current Foldback; Low Noise; No External Capacitor needed; Efficiency to 83%
中文描述： 過(guò)濾含視頻色度，同步信號(hào)處理LSI兼容NTSC制式/ PAL制
文件頁(yè)數(shù)： 13/44頁(yè)
文件大?。?/td> 338K
代理商： UPC1830
μ
PC1830
13
5. BLOCK OPERATION
5.1 Video Signal Processing Section
(1) Input signal
After coupling by a capacitor (0.22
μ
F), a 1 V
p-p
composite video signal is input to the composite video signal input
pin (pin 36).
(2) Clamp circuit
The clamp circuit controls the pedestal voltage level to be constant to make it a reference voltage for the post-stage
signal processing.
(3) Chroma trap circuit
Eliminates the chroma signal (NTSC system: approximately 3.58 MHz, PAL system: approximately 4.43 MHz) from
a composite video signal and extracts a brightness signal.
(4) Separate/composite switching circuit
Operates as shown in Table 5-1 according to the voltage of the separate chroma input pin (pin 34).
Table 5-1. Operation when Switching Separate/Composite Signals
Separate chroma input
pin (pin 34) voltage
Mode
Brightness signal
processing
ACC amp input
Less than 3.7 V
Y/C separate input
Without chroma trap
Input from separate chroma
3.7 V or higher
Composite video input
With chroma trap
Input from chroma BPF
(5) Delay circuit
Compensates for the delay between the brightness signal and chroma signal by delaying the brightness signal.
(6) Contrast adjustment circuit
Adjusts the amplitude of the brightness signal output from the Y output pin (pin 12) according to the voltage of the
contrast control pin (pin 38).
The control characteristic is shown in Figure 5-1.
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