- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄382720 > UCB1500 (NXP SEMICONDUCTORS) PCI to AC97 bridge/host controller PDF資料下載
參數(shù)資料
| 型號： | UCB1500 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI to AC97 bridge/host controller |
| 中文描述： | PCI BUS CONTROLLER, PQFP80 |
| 封裝： | 12 X 12 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-315-1, LQFP-80 |
| 文件頁數(shù)： | 15/58頁 |
| 文件大小： | 1001K |
| 代理商： | UCB1500 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁當前第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁
Philips Semiconductors
UCB1500
PCI to AC97 bridge/host controller
Objective specification
Rev. 01 — 4 February 2000
15 of 58
9397 750 06854
Philips Electronics N.V. 2000. All rights reserved.
[07-06]: Status Register
[08]: Revision ID (read only):
Current revision of chip = 1.
[0B-09]: Class Code Register (read only):
Value = 040100h for multimedia device,
audio. Programmable through EEPROM interface or register 47-45h.
[0C]: Cache Line Size (read only):
Always 0; no cache supported.
[0D]: Latency Timer
[0E]: Header Type (read only):
Always 0.
Table 16: Status Register bit description
Bit
Description
15
PERR detected
Set to ‘1’ whenever parity error is detected. Write ‘1’ to clear.
14
SERR asserted
Set to ‘1’ if UCB1500 asserted SERR. Write ‘1' to clear.
13
Received master abort
If set, UCB1500 has received master abort during its slave operation. Write ‘1’ to
clear.
12
Received target abort
If set, UCB1500 has received target abort during its master operation. Write `1'
to clear
11(r)
Target abort
Always ‘0’; UCB1500 never signals target abort.
10-9(r)
Timing
Always 01b; wait state during slave access to UCB1500.
8
PERR reported
Not implemented, always 0.
7(r)
Fast back-to-back capable
Always ‘1’; NO wait state between PCI cycles.
6(r)
User Definable features
Always ‘0’; device does not support user definable features.
5(r)
66 MHz capable bit
Always ‘0’; device is 33 MHz device only.
4(r)
Capabilities bit
(read only)
Always ‘1’; capabilities present.
3-0
Reserved.
Table 17: Latency Timer register bit description
Bit
Description
7-4
Latency Timer
Bits 7-4 of the latency timer, in units of PCI clocks * 16.
3-0(r)
Latency Timer
Bits 3-0 of the latency timer. These bits are read only and are always 0000b,
giving timer granularity of 16 PCI clocks.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| UCC1913D | Very low drop voltage regulators with inhibit |
| UCC1913DTR | Analog IC |
| UCC1913J | Very low drop voltage regulators with inhibit |
| UCC1913N | Very low drop voltage regulators with inhibit |
| UCC1926DS | Very low drop voltage regulators with inhibit |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| UCB1510 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:AC97 digital modem codec |
| UCB15-101T-RC | 制造商:ALLIED 制造商全稱:Allied Components International 功能描述:Ultra Current Beads |
| UCB1510DB | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:AC97 digital modem codec |
| UCB15-121T-RC | 制造商:ALLIED 制造商全稱:Allied Components International 功能描述:Ultra Current Beads |
| UCB15-600T-RC | 制造商:ALLIED 制造商全稱:Allied Components International 功能描述:Ultra Current Beads |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。