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參數(shù)資料
| 型號： | UAA3522HL |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 無繩電話/電話 |
| 英文描述： | Low power dual-band GSM transceiver with an image rejecting front-end |
| 中文描述： | TELECOM, CELLULAR, RF FRONT END CIRCUIT, PQFP48 |
| 封裝： | 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-313-2, LQFP-48 |
| 文件頁數(shù)： | 8/28頁 |
| 文件大?。?/td> | 148K |
| 代理商： | UAA3522HL |
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2000 Feb 18
8
Philips Semiconductors
Objective specification
Low power dual-band GSM transceiver
with an image rejecting front-end
UAA3522HL
The synthesizer, receiver and transmitter cannot all be on
at the same time. Table 1 shows which parts of the device
are enabled (on) or disabled (off) in each mode.
Table 1
Operating modes
The synthesizer includes the oscillators and LO buffers
commontothereceiveandtransmitsections.Thereceiver
includes the RF section and the I/Q demodulator. When
the receiver is on, the LNA can be switched off to allow
DC offset compensation to be performed. The RF section
canalsobeswitchedoffforDCS applications.SeeSection
“Receiver power status control”.
R
ECEIVER POWER STATUS CONTROL
DC offset compensation: This feature allows the DC
offset of the receiver output to be set accurately. When
the receiver is on, the LNA can be switched off to isolate
the antenna input from the I/Q demodulator input.
The offset at the I and Q outputs can be independently
reduced to less than 50 mV by adequately programming
two 5-bit data registers, see Table 4 “Register bit
allocation”. The LNA is switched on or off by the status
of bit LNA (see Table 2).
Disabling RF section: For DCS applications, the RF
section can be disabled in RX mode. The same
IF circuits are used for both GSM and DCS applications
to avoid duplication. For DCS applications using the
UAA2077XM, for example, the RF section of the
UAA3522HL does not have to be powered on.
The RF section is enabled or disabled by the status of
bit RF when the RX mode is activated (see Table 3).
Table 2
Bit LNA status
Table 3
Bit RF status
Programming
S
ERIAL PROGRAMMING BUS
A simple 3-wire unidirectional serial bus is used for
programming the IC. The lines are called DATA, CLK
and EN (enable). Programming data is sent to the IC in
bursts which are separated from each other by EN.
Programming clock edges are ignored until EN goes
activeLOW.Thedataisloadedintotheaddressedregister
when EN returns inactive HIGH, and when the CLK is in
either state, without affecting the data in the register.
The register only holds the last 18 bits that are serially
clocked into the IC.
Additional leading bits are ignored, and no check is made
on the number of clock pulses received. The fully static
CMOS design uses virtually no current when the bus is
inactive. It can always accept new programming data even
when both synthesizers are powered-off.
D
ATA FORMAT
Data is loaded into the register with the most significant bit
(MSB) first. The first 14 bits are data, while the last 4 bits
are the register address. The address bits are decoded on
the rising edge of EN. This internally generates a load
pulse to store the data in the addressed register.
To ensure that data loads correctly after the device has
powered-up,ENshouldbeheldLOWandonlytakenHIGH
after the appropriate register has been loaded.
The EN pulse is inhibited during the period when data is
read by the frequency dividers to prevent divider ratio data
from being read incorrectly. This state is guaranteed by
always allowing for a minimum EN pulse width after data
transfer.
MODE
POWER STATUS
SYNTHESIZER RECEIVER TRANSMITTER
Idle
SYN
RX
TX
off
on
on
on
off
off
on
off
off
off
off
on
BIT LNA STATUS
POWER STATUS OF BIT
LNA
0
1
off
on
BIT RF STATUS
POWER STATUS OF
RECEIVER RF SECTION
IN RX MODE
1
0
on (GSM)
off (DCS)
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| UAA3540TS | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:DECT receiver |
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