參數(shù)資料
型號(hào): TVP6000CPFP
廠商: Texas Instruments, Inc.
英文描述: NTSC/PAL Digital Video Encoder
中文描述: NTSC / PAL數(shù)字視頻編碼器
文件頁數(shù): 47/57頁
文件大?。?/td> 268K
代理商: TVP6000CPFP
2–35
2.11.46 HDTAH
Subaddress: 9A
7
6
5
4
3
2
1
0
HDTA[15:8]
Where:
HDTA[15:8]Horizontal over-scan compensation ratio. The LSB of this field is located in the
HDTAL register. Refer to the description of HDTAL for more information.
2.11.47 VOFS
Subaddress: 9B
7
6
5
4
3
2
1
0
VOFS[7:0]
Vertical offset
Where:
VOFS[7:0] Vertical offset of the scaled image on the screen in lines from beginning of the field.
This register is used with HOFS register to position the scaled image on the screen.
Vertical offset is given in units of two scan lines in a field or four scan lines in a
frame.
2.11.48 HOFS
Subaddress: 9C
7
6
5
4
3
2
1
0
HOFS[7:0]
Horizontal offset
Where:
HOFS[7:0] Horizontal offset of the scaled image on the screen in pixels from the beginning of the
scan line. Used with VOFS register to position the scaled image on the screen.
Horizontal offset is given in units of four pixels.
2.11.49 NLR
Subaddress: 9D
7
6
5
4
3
2
1
0
NLR[7:0]
New line request
Where:
NLR[7:0]
The minimum number of LLC clock delays between the trailing edge of NEWLINE
and the leading edge of REQUEST. The value must be sufficiently large to give the
graphics controller enough time to supply pixel data when REQUEST is asserted.
2.11.50 TEST1, TEST2, TEST3
Subaddress: 9E, 9F, A0
These three register are reserved for chip test purposes only. No applications should access them.
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