參數(shù)資料
型號： TVP6000CPFP
廠商： Texas Instruments, Inc.
英文描述： NTSC/PAL Digital Video Encoder
中文描述： NTSC / PAL數(shù)字視頻編碼器
文件頁數(shù)： 40/57頁
文件大?。?/td> 268K
代理商： TVP6000CPFP
2–28
2.11.22 HTRIGGER0
Subaddress: 6E Default: 0xE0
7
6
5
4
3
2
1
0
HTRIG[7:0]
Where:
HTRIG[7:0] Least significant bit of horizontal trigger phase setting for RCV1 and RCV2 as inputs.
HTRIG is expressed in half-pixels or clk2x periods.
2.11.23 HTRIGGER1
Subaddress: 6F Default: 0x8C
7
6
5
4
3
2
1
0
HTRIG[10:8]
Where:
HTRIG[10:8] Most significant bit of horizontal trigger phase setting for RCV1 and RCV2 as
inputs. HTRIG is expressed in half-pixels or clk2x periods.
2.11.24 VTRIGGER
Subaddress: 70 Default: 0xC0
7
6
5
4
3
2
1
0
PRESA
PRESB
SBLANK
VTRIG[4:0]
Where:
PRESA
PRESB
Phase reset A. Used as shown in Table 2–20.
Phase reset B. Used as shown in Table 2–20. These two bits decide how frequently
the color subcarrier is reset to CPHS (subaddress 5A). GLCE is bit 3, subaddress 61.
Vertical blanking setting
0
Vertical blanking is defined by the settings of the FAL and LAL registers
1
Vertical blanking is forced automatically during field synchronization and
equalization.
VTRIG[4:0] Vertical trigger reference for pin RCV1. These bits specify where on a field of sixteen
lines the RCV1 pin is triggered. The VTRIG field is expressed in units of a half line.
SBLANK
Table 2–20. Phase Reset Modes
GLCE
PRESA
PRESB
PHASE RESET MODE
0
0
0
No reset
0
0
1
Reset every two lines
0
1
0
Reset every eight fields
0
1
1
Reset every four fields
1
X
X
Reset by reset bit on GLCI pin
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參數(shù)描述
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