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參數(shù)資料
| 型號： | TVP3026-250AMDN |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Video Interface Palette |
| 中文描述： | 視頻接口面板 |
| 文件頁數(shù)： | 95/107頁 |
| 文件大?。?/td> | 513K |
| 代理商： | TVP3026-250AMDN |
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C–1
Appendix C
Recommended Clock Programming Procedures
The following procedures are recommended for programming the TVP3026 PLLs. In a typical system, many
combinations of resolution and refresh rates are possible. The PLLs must be able to switch between any
two of these frequencies. It is difficult to test all possible combinations. In order to reduce the possibility of
error, it is recommended that the PLL is reset prior to programming. This causes the voltage controlled
oscillator (VCO) to stop oscillating prior to searching for the new programmed frequency. When this is done,
the frequency search always begins at the same point and the possibility for error is greatly reduced.
MCLK PLL
This is the simplified method of programming the MCLK PLL. If the system does not allow MCLK to be
stopped or is sensitive to transition effects on MCLK, the procedure described in Section 2.4.2.1 can be used
instead.
1.
Disable MCLK PLL (PLLEN bit = 0).
2.
Program MCLK PLL N, M, and P registers (with PLLEN bit = 1) for new frequency.
VGA Mode Setup
1.
Set loop clock PLL PLLEN bit to 0.
2.
Set pixel clock PLL PLLEN bit to 0.
3.
Set PLLSEL(1, 0) bits to 1x. (This causes programmed PLLEN bits to take effect. VCOs are
stopped.)
4.
Set PLLSEL(1, 0) bits to 00 (25.057 MHz) or 01 (28.686 MHz).
Table C–1. Programming Procedure – VGA Mode Setup
Index
Data
Comment
1A
77
Select CLK0 as clock source. Set bits 6–4 to disable
unused VCLK output.
18, 19
80, 98
VGA mode
2C
2A
Point to P registers
2F
0
Set loop clock PLL PLLEN bit to 0
2D
0
Set pixel clock PLL PLLEN bit to 0
PLLSEL(1, 0)
11
Causes programmed PLLEN bits to take effect. VCOs
are stopped.
PLLSEL(1, 0)
00 (for 25.057 MHz)
01 (for 28.636 MHz)
Select one of the hard-wired VGA pixel clock PLL
settings.
39
1. These procedures show the order of programming that should be used for programming the clocks and
related registers. The complete mode setup may require other registers to be programmed also.
2. In standard VGA modes, the PLLSEL(1,0) inputs select the pixel clock PLL fixed frequency settings (25.057
MHz or 28.636 MHz). The loop clock PLL is normally reset and the pixel clock PLL is routed to the RCLK
output.
18
Pixel clock PLL routed to RCLK terminal (see Note 2).
NOTES:
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TVP3026-250APCE | Video Interface Palette |
| TVP3026-250BMDN | Video Interface Palette |
| TVP3026-135AMDN | Video Interface Palette |
| TVS524SM | Transient Voltage Suppressor |
| TVS410 | TRANSIENT VOLTAGE SUPPRESORS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TVP3026-250APCE | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
| TVP3026-250BMDN | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
| TVP3026-250BPCE | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述: |
| TVP3026-250CPCE | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TVP3026-250MDN | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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