參數(shù)資料
型號: TVP3026-250AMDN
廠商: Texas Instruments, Inc.
英文描述: Video Interface Palette
中文描述: 視頻接口面板
文件頁數(shù): 63/107頁
文件大小: 513K
代理商: TVP3026-250AMDN
3–3
3.4 Operating Characteristics
PARAMETER
TEST CONDITIONS
8/6 high
MIN
TYP
MAX
UNIT
Resolution (each DAC)
8
bits
8/6 low
6
EL
End-point linearity error
(each DAC)
8/6 high
1
LSB
8/6 low
1/4
ED
Differential linearity error
(each DAC)
8/6 high
1
LSB
8/6 low
1/4
Gray scale error
5%
White level relative to blank
17.69
19.05
20.4
mA
White level relative to black
(7.5 IRE only)
16.74
17.62
18.5
mA
Black level relative to blank
(7.5 IRE only)
0.95
1.44
1.9
mA
Output current (see Note 2)
Blank level on IOR, IOB
0
5
50
μ
A
Blank level on IOG
(with SYNC enabled)
6.29
7.6
8.96
mA
Sync level on IOG (with
SYNC enabled)
0
5
50
μ
A
One LSB (8/6 high)
69.1
μ
A
μ
A
One LSB (8/6 low)
276.4
DAC-to-DAC matching
2%
5%
DAC-to-DAC crosstalk
–20
dB
Output compliance
–1
1.2
V
Voltage reference output voltage
1.15
1.235
1.26
V
k
pF
Output impedance
50
Output capacitance
f = 1 MHz,
IOUT = 0
13
Sense voltage reference
300
350
400
mV
Clock and data feedthrough
–20
dB
Glitch area (see Note 3)
50
pV–s
Pipeline delay, VGA port
18
DOTCLK
periods
Pipeline delay, pixel port (see Note 4)
18
DOTCLK
periods
Lock time
5
ms
Pixel clock PLL,
MCLK PLL
Jitter
200
ps
NOTES:
2. Test conditions for RS343-A video signals (unless otherwise specified), see Section 3.2, Recommended
Operating Conditions using external voltage reference Vref = 1.235 V, RSET = 523
. When using the
internal voltage reference, RSET may need to be adjusted in order to meet these limits.
3. Glitch area does not include clock and data feedthrough. The – 3-dB test bandwidth is twice the clock rate.
4. Pipeline delay from pixel port depends on Latch Control Register setting. Value shown is for LCR = 0x06.
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