參數(shù)資料
型號(hào): TVP3026-250AMDN
廠商: Texas Instruments, Inc.
英文描述: Video Interface Palette
中文描述: 視頻接口面板
文件頁(yè)數(shù): 92/107頁(yè)
文件大?。?/td> 513K
代理商: TVP3026-250AMDN
B–2
The resulting divide ratios and clock frequencies are illustrated in Figure B–2.
÷
32
Phase
Detector
Charge
Pump
VCO
OUT
Dot Clock
LCLK
÷
4
5.3 MHz
5.3 MHz
170 MHz
21.25 MHz
N = 33
(65 –N = 32)
M = 61
(65 –M = 4)
÷
2
÷
2
TVP3026
Loop Clock PLL
42.5 MHz
÷
2
GUI Accelerator
42.5 MHz
21.25 MHz
Up
Down
K = 2
170 MHz
85 MHz
P = 1
(2P = 2)
Q = 0
[Q +1] = 2)
(2
Figure B–2. Loop Clock PLL Example
Pixel Clock and MCLK PLLs
The internal structure used for the pixel clock and MCLK PLLs is shown in Figure B–3. These PLLs
synthesize the pixel clock and MCLK frequencies. The reference clock can be either a resonant crystal or
can be driven with a TTL level signal. The phase detector performs phase comparison at the rising edge
of the received clocks after the N and M prescalers. The charge pump and loop filter generate an analog
control signal to the VCO. The VCO frequency is then divided by the P post-scalar. The P post-scalar
provides division ratios of 1, 2, 4, or 8. The output from the pixel clock PLL or the loop clock PLL may be
selected for output on the RCLK terminal. The output from the MCLK PLL or the internal dot clock (to provide
a smooth transition on MCLK) may be selected for output on the MCLK terminal. The same PLL register
values may be used for the pixel clock PLL or MCLK PLL as long as the output frequency of the MCLK PLL
does not exceed 100 MHz.
1
65–N
Phase
Detector
1
65–M
Charge
Pump
VCO
1
2P
1
8
OUT
Ref Clock
Up
Down
Figure B–3. Pixel Clock and MCLK PLL Structure
As a programming example, we can consider programming the pixel clock PLL for a mode using a 170 MHz
pixel clock. Since the reference clock is the common 14.31818 MHz crystal, the register values in
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