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參數(shù)資料
| 型號： | TUA6100B6 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | Components for Satellite Receiver Units |
| 中文描述： | 元件衛(wèi)星接收單元 |
| 文件頁數(shù)： | 19/46頁 |
| 文件大?。?/td> | 819K |
| 代理商： | TUA6100B6 |
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Preliminary Specification
TUA6100B6
High-Frequency-Products
14
26.1.01
8.12.3 Divide ratio programming
Because of DCR concept the tuning frequency of the RF input controlled by the PLL is given below:
rf :
ri :
P :
A :
N :
R :
M = (P N)+A : total divide ratio of the PLL (with A<N)
frequency of RF
input
reference frequency input (crystal oscillator)
divide ratio of the prescaler [ P/(P+1) = (32/33) or (64/65) ]
divide ratio of the A-counter (max. 7 bit)
divide ratio of the N-counter (max. 11 bit)
divide ratio of the R-counter (max. 10 bit)
Note :
for continuous frequency steps following condition is necessary
8.12.4 Phase detector outputs
rf
P N
A
+
ri
R
---
M
R
---- ri
with
A
N
=
=
P N
A
+
P
P
1
–
PD
Polarity
pos.
PD
Polarity
neg.
f
R
f
V
P-Channel (I+)
Tri-State.
N-Channel (I-)
P-Channel (I+)
Tri-State.
N-Channel (I-)
Frequency f
V
> f
R
or f
V
leading
Frequency f
V
= f
R
(PLL is locked)
Frequency f
V
< f
R
or f
V
lagging
UP
Polarity
pos.
DOWN
Polarity
pos.
(internal Signal)
(internal Signal)
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