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參數(shù)資料
| 型號(hào)： | TUA6100B6 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | Components for Satellite Receiver Units |
| 中文描述： | 元件衛(wèi)星接收單元 |
| 文件頁數(shù)： | 15/46頁 |
| 文件大?。?/td> | 819K |
| 代理商： | TUA6100B6 |
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Preliminary Specification
TUA6100B6
High-Frequency-Products
10
26.1.01
8.12 Synthesizer PLL
Parameter see
Synthesizer Phase detector Charge pump output / Loop filter input
and
Synthesizer PLL
(
page 25
).
The PLL block forms a digitally programmable
p
hase
l
ocked
l
oop (PLL) with a serial bus control.
The circuit consists of a serial control logic, a high frequency dual modulus prescaler, an A- and
a N-counter with dual modulus control logic, a reference- (R-) counter, and a phase detector with
lock detector and charge pump output.
8.12.1 Serial Bus Control Logic
For TUA6100 the combi-bus is selectable between I
2
C and 3-wire-busmode by pin
BUSMODE ( I
2
C = low, 3W = high ).
All bus pins (CLOCK, DATA, ENABLE and BUSMODE) are Schmitt-triggered with input buffer for
3V or 5V C.
Programming of the IC is done by a serial data protocol with sub addressing. The contents of the
message is assigned to the functional units according to the preceded sub addresses.
Before programming the counters the control register (sub address 00
Hex
) should be set.
The data bit stream starts with the most significant bit (MSB) and is shifted in on the low to high
transition of the clock signal.
I
2
C bus mode
In this mode four different chip addresses can be set by appropriate DC level at pin ENABLE which has
in this case the function of a
c
hip
a
ddress
s
elect (CAS). The pin DATA is a bidirectional input/output pin
for
s
erial
da
ta (SDA) from and the acknowledge bit (ACK) to the microcontroller (μC).
Data Transition:
Data transition on the pin DATA must only occur when the
s
erial
cl
ock (SCL) is low.
SDA transitions while SCL is high will be interpreted as start or stop condition.
Start Condition (STA):
A start condition is defined by a high to low transition of the SDA line while SCL is at a stable high
level.This start condition must precede any command and initiate a data transfer onto the bus.
Stop Condition (STO):
A stop condition is defined by a low to high transition of the SDA while the SCL line is at a stable
high level. This condition terminate the communication between the devices and forces the bus
interface into the initial conditions.
Acknowledge (ACK):
Indicates a successful data transfer. The transmitter will release the bus after sending 8 bit of data.
During the 9th clock cycle the receiver will pull the SDA line to low level to indicate it has received
the 8 bits of data correctly.
Data Transfer Write Mode:
To start the communication, the bus master must initiate a start condition, followed by the 8bit chip
address (write). The chip address for the TUA 6100 is fixed as ”11000xyz” (MSB at first).
The last significant bit (LSB=z) of the chip address byte defines the type of operation to be
performed: z=1 means, a read operation is selected and z=0 means, a write operation is selected.
After the successful comparison of the transmitted chip address with the fixed one include the
hard-switched chip address select bits CAS2=x and CAS1=y, the serial control logic of the TUA6100
will generate an ACK. Otherwise the processor must break off the data transfer.
After this device addressing the desired subaddress byte and data bytes must be followed. The
subaddresses determines which one of the data bytes (00H...03H) is transmitted first.
At the end of the data transition the master must generate the stop condition.
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