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參數(shù)資料
| 型號： | TUA6100B6 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | Components for Satellite Receiver Units |
| 中文描述： | 元件衛(wèi)星接收單元 |
| 文件頁數(shù)： | 16/46頁 |
| 文件大?。?/td> | 819K |
| 代理商： | TUA6100B6 |
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Preliminary Specification
TUA6100B6
High-Frequency-Products
11
26.1.01
Data Transfer Read Mode:
To start the communication in the read mode, the bus master must initiate a start condition,
followed by the 8bit chip address (write: z=0) and by the subaddress (80H) of the read register.
Then followed by the chip address (read: z=1). After that procedure the 8bit data register 80H
is read out. When the first byte(s) read out the μC mandatory send LOW during the ACK-clock, but
after the last byte is read out the μC mandatory send HIGH (neg. ACK) during the ACK-clock.
At the end of data transition the master must be generate the stop condition.
3-wire bus mode
Pin DATA is in this mode only data input. There is no data output. Pin ENABLE is used to activate the
bus interface and to allow the transfer of data to the device. When ENABLE is in an inactive high state,
shifting is inhibited.
Data Transition:
Data transition on the pin DATA must only occur when the clock SCL is low. To transfer data to
the device, ENABLE (which must start inactive high) is taken low. A serial data transfer is made
via DATA and CLOCK when ENABLE is taken back high. The bit stream doesn’t need a chip
address.
Data Transfer Write Mode:
To start the communication, the signal ENABLE is taken low. The desired subaddress byte and
data bytes must be followed. The subaddresses determines which one of the data bytes (00H...03H)
is transmitted first. At the end of the data transition the bus ENABLE must be high.
Data Transfer Read Mode:
To start the communication in the read mode, the ENABLE is taken low, followed by the subaddress
read (xxH). After that the device is ready to read out the xbit data register xxH. At the end of the
data transition the ENABLE must be high.
Dual Modulus Prescaler
The dual modulus prescaler up to 2.5 GHz is switchable between divide ratio 32/33 and 64/65 by the
bit D22 in the A/N-counter subaddress (01H). Input frequency of the prescaler is the divided
GHz-VCO-frequency
4 with the range of 950 MHz .. 2150 MHz.
R-Counter and A- / N-Counter
The TUA 6100 has a 10-bit counter for the R-path and a 7-bit and 11-bit counter for the A-/N-path.
The input frequency for the R-counter is the buffered XTAL-frequency (1-16 MHz). Tuning steps can be
selected by the programmable R-counter from f
R
= 31.25 kHz ..1 MHz (f
XTAL
=16MHz).
The output frequency of the prescaler (14 MHz..70 MHz) passes the programmable dual modulus
A-/N-counter which switches the prescaler and make available the comparison frequency f
V
for the
digital frequency / phase detector.
Phase Comparator (Frequency/Phase Detector)
The digital phase and frequency sensitive phase detector generates a phase error signal UP or DOWN
according to the phase difference between f
R
(R-counter output) and f
V
(N-counter output).
This phase error signal drives the charge pump current generator.
Polarity is changeable via bus (bit D4 of the control register), it must be negative for TUA6100
application note.
If the positive edge of the divided VCO signal appears prior to the positive edge of the reference signal,
the DOWN-output pulses for the duration of the phase difference.
In the reverse case the UP-output pulses.
If the two signals are in phase (PLL is locked), the phase detector produces an output signal with fixed
anti-backlash impulses in order to prevent a dead zone for very small phase deviations.
Therefore phase differences of less than 100 ps can be resolved.
In general the shortest anti-backlash pulse gives the best system performance.
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