參數(shù)資料
型號： TSC251G2DXXX-24CED
英文描述： IC CYCLONE III FPGA 80K 484 FBGA
中文描述： 微控制器
文件頁數(shù)： 55/63頁
文件大?。?/td> 878K
代理商： TSC251G2DXXX-24CED
Rev. A - May 7, 1999
55
TSC80251G2D
11.8 AC Characteristics - External Clock Drive and Logic Level References
Definition of symbols
Table 59. External Clock Timing Symbol Definitions
Timings
Table 60. External Clock AC Timings; V
DD
= 4.5 to 5.5 V, T
A
= -40 to +85
°
C
Waveforms
Figure 33. External Clock Waveform
Note:
During AC testing, all inputs are driven at V
DD
-0.5 V for a logic 1 and 0.45 V for a logic 0.
Timing measurements are made on all outputs at V
IH
min for a logic 1 and V
IL
max for a logic 0.
Figure 34. AC Testing Input/Output Waveforms
Note:
For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV
change from the loading V
OH
/V
OL
level occurs with I
OL
/I
OH
=
±
20 mA.
Figure 35. Float Waveforms
Signals
Conditions
C
Clock
H
High
L
Low
X
No Longer Valid
Symbol
Parameter
Min
Max
Unit
F
OSC
T
CHCX
T
CLCX
T
CLCH
T
CHCL
Oscillator Frequency
24
MHz
High Time
10
ns
Low Time
10
ns
Rise Time
3
ns
Fall Time
3
ns
0.45 V
T
CLCL
V
DD
- 0.5
V
IH1
V
IL
T
CHCX
T
CLCH
T
CHCL
T
CLCX
0.45 V
V
DD
- 0.5
0.2 V
DD
+ 0.9
0.2 V
DD
- 0.1
V
IH
min
V
IL
max
INPUTS
OUTPUTS
V
LOAD
V
OH
- 0.1 V
V
OL
+ 0.1 V
V
LOAD
+ 0.1 V
V
LOAD
- 0.1 V
Timing Reference Points
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