參數(shù)資料
型號: TSB41AB3
英文描述: IC APEX 20KE FPGA 400K 672-FBGA
中文描述: 3個IEEE 1394a端口電纜收發(fā)器/仲裁器
文件頁數(shù): 32/50頁
文件大小: 662K
代理商: TSB41AB3
SLLS418G
JUNE 2000
REVISED JANUARY 2003
32
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
output differentiation (continued)
0
1
1
0
0
0
0
1
0
L
H
Z
0
Z
Z
L
H
Z
Logic State
Signal Level
Figure 14. Signal Transformation for Digital Differentiation
The TSB41AB3 implements differentiation circuitry functionally equivalent to that shown in Figure 15 on the
bidirectional CTL0
CTL1and D0
D7 terminals. The TSB41AB3 also implements an input hysteresis buffer on
the LREQ input to convert this signal to the correct logic level when differentiated. The LLC must also implement
similar output differentiation and input hysteresis circuitry on its CTL and D terminals, and output differentiation
circuitry on its LREQ terminal.
DIn
To/From Internal
Device Logic
DOut
ISO
OutEn
Init
SysClk
D
Q
D
Q
D
Q
D
3-State Output
Driver
Input Buffer With
Hysteresis
Figure 15. Input/Output Differentiation Logic
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