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參數資料
| 型號： | TSB41AB3 |
| 英文描述： | IC APEX 20KE FPGA 400K 672-FBGA |
| 中文描述： | 3個IEEE 1394a端口電纜收發(fā)器/仲裁器 |
| 文件頁數： | 2/50頁 |
| 文件大小： | 662K |
| 代理商： | TSB41AB3 |
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SLLS418G
–
JUNE 2000
–
REVISED JANUARY 2003
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description
The TSB41AB3 provides the digital and analog transceiver functions required to implement a three-port node
in a cable-based IEEE 1394 network. Each cable port incorporates two differential line transceivers. The
transceivers include circuitry to monitor the line conditions as needed for determining connection status, for
initialization and arbitration, and for packet reception and transmission. The TSB41AB3 is designed to interface
with a line layer controller (LLC), such as the TSB12LV21, TSB12LV22, TSB12LV23, TSB12LV26, TSB12LV31,
TSB12LV41, TSB12LV42, or TSB12LV01A.
The TSB41AB3 requires only an external 24.576-MHz crystal as a reference. An external clock may be used
instead of a crystal. An internal oscillator drives an internal phase-locked loop (PLL), which generates the
required 393.216-MHz reference signal. This reference signal is internally divided to provide the clock signals
used to control transmission of the outbound encoded strobe and data information. A 49.152-MHz clock signal
is supplied to the associated LLC for synchronization of the two chips and is used for resynchronization of the
received data. The power-down (PD) function, when enabled by asserting the PD terminal high, stops operation
of the PLL.
The TSB41AB3 supports an optional isolation barrier between itself and its LLC. When the ISO input terminal
is tied high, the LLC interface outputs behave normally. When the ISO terminal is tied low, internal differentiating
logic is enabled, and the outputs are driven such that they can be coupled through a capacitive or transformer
galvanic isolation barrier as described in Annex J of IEEE Std 1394-1995 and in the 1394a-2000 Supplement
(section 5.9.4) (hereinafter referred to as Annex J type isolation). To operate with TI bus holder isolation, the
ISO terminal on the PHY must be high.
Data bits to be transmitted through the cable ports are received from the LLC on two, four, or eight parallel paths
(depending on the requested transmission speed). They are latched internally in the TSB41AB3 in
synchronization with the 49.152-MHz system clock. These bits are combined serially, encoded, and transmitted
at 98.304, 196.608, or 392.216 Mbits/s (referred to as S100, S200, and S400 speed, respectively) as the
outbound data-strobe information stream. During transmission, the encoded data information is transmitted
differentially on the TPB cable pair(s), and the encoded strobe information is transmitted differentially on the
TPA cable pair(s).
During packet reception the TPA and TPB transmitters of the receiving cable port are disabled, and the receivers
for that port are enabled. The encoded data information is received on the TPA cable pair, and the encoded
strobe information is received on the TPB cable pair. The received data-strobe information is decoded to recover
the receive clock signal and the serial data bits. The serial data bits are split into two-, four-, or eight-bit parallel
streams (depending upon the indicated receive speed), resynchronized to the local 49.152-MHz system clock,
and sent to the associated LLC. The received data is also transmitted (repeated) on the other active (connected)
cable ports.
Both the TPA and TPB cable interfaces incorporate differential comparators to monitor the line states during
initialization and arbitration. The outputs of these comparators are used by the internal logic to determine the
arbitration status. The TPA channel monitors the incoming cable common-mode voltage. The value of this
common-mode voltage is used during arbitration to set the speed of the next packet transmission. In addition,
the TPB channel monitors the incoming cable common-mode voltage on the TPB pair for the presence of the
remotely supplied twisted-pair bias voltage.
The TSB41AB3 provides a 1.86-V nominal bias voltage at the TPBIAS terminal for port termination. The PHY
contains three independent TPBIAS circuits. This bias voltage, when seen through a cable by a remote receiver,
indicates the presence of an active connection. This bias voltage source must be stabilized by an external filter
capacitor of 1
μ
F.
The line drivers in the TSB41AB3, operating in a high-impedance current mode, are designed to work with
external 112-
line-termination resistor networks in order to match the 110-
cable impedance. One network
is provided at each end of a twisted-pair cable. Each network is composed of a pair of series-connected 56-
resistors. The midpoint of the pair of resistors that is directly connected to the twisted-pair A terminals is
相關PDF資料 |
PDF描述 |
|---|---|
| TSB41BA3-EP | IC APEX 20KE FPGA 400K 672-FBGA |
| TSB41LV03PFP | IC APEX 20KE FPGA 600K 652-BGA |
| TSB41AB2I | IEEE 1394a-2000 TWO-PORT CABLE TRANSCEVER/ARBITER |
| TSB41LV03AI | IEEE 1394a THREE-PORT CABLE TRANSCEIVER/ARBITER |
| TSC692E | 672-pin FineLine BGA |
相關代理商/技術參數 |
參數描述 |
|---|---|
| TSB41AB3-EP | 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE 1394A-2000 THREE-PORT CABLE TRANSCEIVER/ARBITER |
| TSB41AB3IPFP | 功能描述:緩沖器和線路驅動器 Three-Port Cable Xcvr/Arbiter RoHS:否 制造商:Micrel 輸入線路數量:1 輸出線路數量:2 極性:Non-Inverting 電源電壓-最大:+/- 5.5 V 電源電壓-最小:+/- 2.37 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Reel |
| TSB41AB3IPFP | 制造商:Texas Instruments 功能描述:IC TRX/ARBITER 1394A 3 PORT 80HTQFP |
| TSB41AB3IPFPEP | 功能描述:1394 接口集成電路 Mil Enh 3-Port Cable Xcvr/Arbiter RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB41AB3IPFPG4 | 制造商:Texas Instruments 功能描述:THREE PORT CBL TRNSCVR/ARBITER 1TX 1RX 400MBPS 80HTQFP - Rail/Tube |
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