參數(shù)資料
型號: TS83102G0BMGS
廠商: E2V TECHNOLOGIES PLC
元件分類: ADC
英文描述: 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CBGA152
封裝: 21 X 21 MM, 1.27 MM PITCH, HERMETIC SEALED, CERAMIC, CGA-152
文件頁數(shù): 35/54頁
文件大小: 2622K
代理商: TS83102G0BMGS
40
0935B–BDC–06/08
TS83102G0BMGS
e2v semiconductors SAS 2008
9.4.1
Differential Clock Inputs Voltage Levels (0 dBm Typical)
Figure 9-5.
Differential Clock Inputs - Ground Common Mode (Recommended)
9.4.2
Equivalent Single-ended Clock Input Voltage Levels (0 dBm Typical)
Figure 9-6.
Single-ended Clock Inputs - Ground Common Mode
9.5
Noise Immunity Information
The circuit’s noise immunity performance begins at the design level. Efforts have been made on the
design to make the device as insensitive as possible to chip environment perturbations, which may result
from the circuit itself or be induced by external circuitry (cascode stage’s isolation, internal damping
resistors, clamps, internal on-chip decoupling capacitors.)
Furthermore, the fully differential operation from the analog input up to the digital output provides
enhanced noise immunity by common mode noise rejection. The common mode noise voltage induced
on the differential analog and clock inputs is cancelled out by these balanced differential amplifiers.
Moreover, proper active signal shielding has been provided on the chip to reduce the amount of coupled
noise on the active inputs. The analog and clock inputs of the TS83102G0BMGS device have been sur-
rounded by ground pins, which must be directly connected to the external ground plane.
V
+0.23
-0.23
CLK
CLKB
0 V
t
V
+0.32
-0.32
CLK
CLKB
0 V
t
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