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參數(shù)資料
| 型號： | TS83102G0BMGS |
| 廠商： | E2V TECHNOLOGIES PLC |
| 元件分類： | ADC |
| 英文描述： | 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CBGA152 |
| 封裝： | 21 X 21 MM, 1.27 MM PITCH, HERMETIC SEALED, CERAMIC, CGA-152 |
| 文件頁數(shù)： | 28/54頁 |
| 文件大?。?/td> | 2622K |
| 代理商： | TS83102G0BMGS |
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34
0935B–BDC–06/08
TS83102G0BMGS
e2v semiconductors SAS 2008
SFDR
Spurious Free
Dynamic Range
The ratio expressed in dB of the RMS signal amplitude, set at 1 dB below full-scale, to the
RMS value of the next highest spectral component (peak spurious spectral component).
SFDR is the key parameter for selecting a converter to be used in a frequency domain
application (radar systems, digital receiver, network analyzer...). It may be reported in dBc
(i.e., degrades as signal level is lowered), or in dBFS (i.e. always related back to converter
full-scale)
SINAD
Signal to Noise and
Distortion Ratio
The ratio expressed in dB of the RMS signal amplitude, set to 1 dB below full-scale, to the
RMS sum of all other spectral components, including the harmonics except DC
SNR
Signal to Noise Ratio
The ratio expressed in dB of the RMS signal amplitude, set to 1 dB below full-scale, to the
RMS sum of all other spectral components excluding the first five harmonics
SSBW
Small Signal Input
Bandwidth
Analog input frequency at which the fundamental component in the digitally reconstructed
output waveform has fallen by 3 dB with respect to its low frequency value (determined by
FFT analysis) for input at full-scale –10 dB (–10 dBFS)
TA
Aperture Delay
The delay between the rising edge of the differential clock inputs (CLK,CLKB) (zero crossing
point), and the time at which (VIN, VINB) is sampled
TC
Encoding Clock
Period
TC1 = minimum clock pulse width (high) TC = TC1 + TC2
TC2 = minimum clock pulse width (low)
TD1
Time Delay from Data
to Data Ready
General expression is TD1 = TC1 + TDR - TOD with TC = TC1 + TC2 = 1 encoding clock
period
TD2
Time Delay from Data
Ready to Data
General expression is TD1 = TC1 + TDR - TOD with TC = TC1 + TC2 = 1 encoding clock
period
TF
Fall Time
Time delay for the output data signals to fall from 80% to 20% of delta between low level and
high level
THD
Total Harmonic
Distortion
The ratio expressed in dBc of the RMS sum of the first five harmonic components, to the
RMS value of the measured fundamental spectral component
TOD
Digital Data
Output Delay
The delay from the falling edge of the differential clock inputs (CLK, CLKB) (zero crossing
point) to the next point of change in the differential output data (zero crossing) with a
specified load
TPD
Pipeline Delay
The number of clock cycles between the sampling edge of an input data and the associated
output data being made available (not taking in account the TOD). For the JTS8388B the
TPD is 4 clock periods
TR
Rise Time
Time delay for the output data signals to rise from 20% to 80% of delta between the low level
and high level
TRDR
Data Ready Reset
Delay
Delay between the falling edge of the Data Ready output asynchronous Reset signal
(DDRB) and the reset to digital zero transition of the Data Ready output signal (DR)
TS
Settling Time
Time delay to achieve 0.2% accuracy at the converter output when an 80% full-scale step
function is applied to the differential analog input
VSWR
Voltage Standing
Wave
Where S11 is the reflection coefficient of the scattering
matrix. The VSWR over frequency measures the degree of
mismatching between the packaged ADC input impedance (ideally 50
Ω or so) and the
transmission line’s impedance. The packaged ADC input impedance (transmission line and
termination) is controlled so as to ensure VSWR < 1.2 :1 from DC up to 2.5 GHz. A VSWR of
1.2 :1 corresponds to a 0.039 dB insertion loss (20 dB return loss) that is 99% power
transmitted and 1% reflected
Table 8-1.
Definitions of Terms (Continued)
VSWR
1
S11
+
()
1
S11
–
()
÷
=
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相關代理商/技術參數(shù) |
參數(shù)描述 |
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| TS83102G0BVGL | 制造商:e2v technologies 功能描述:ADC SGL 2GSPS 10-BIT PARALLEL 152CBGA - Trays |
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| TS831-3I | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:MICROPOWER VOLTAGE SUPERVISOR RESET ACTIVE LOW |
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