參數(shù)資料
型號(hào)： TS83102G0BMGS
廠商： E2V TECHNOLOGIES PLC
元件分類： ADC
英文描述： 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CBGA152
封裝： 21 X 21 MM, 1.27 MM PITCH, HERMETIC SEALED, CERAMIC, CGA-152
文件頁(yè)數(shù)： 30/54頁(yè)
文件大小： 2622K
代理商： TS83102G0BMGS
36
0935B–BDC–06/08
TS83102G0BMGS
e2v semiconductors SAS 2008
A Master Asynchronous Reset input command DRRB (ECL compatible single-ended input) is available
for initializing the differential Data Ready output signal (DR/DRB). This feature is mandatory in certain
applications using interleaved ADCs or using a single ADC with demultiplexed outputs. Without Data
Ready signal initialization, it is impossible to store the output digital data in a defined order.
When used with e2v’s TS81102G0 1:4/8 8/10 bit DMUX, it is not necessary to initialize Data Ready, as
this device can start on either clock edge.
9.2
Principle of Data Ready Signal Control by DRRB Input Command
9.2.1
Data Ready Output Signal Reset
The Data Ready signal is reset on the DRRB input command’s falling edge, on the ECL logical low level
(–1.8V). DRRB may also be tied to V
EE = –5V for the Data Ready output signal master reset. As long as
DRRB remains at a logical low level, (or tied to V
EE = –5V), the Data Ready output remains at a logical
zero and is independent of the external free-running encoding clock.
The Data Ready output signal (DR/DRB) is reset to a logical zero after TRDR.
TRDR is measured between the –1.3V point of the DRRB input command’s falling edge and the zero
crossing point of the differential Data Ready output signal (DR/DRB).The Data Ready Reset command
may be a pulse of 1 ns minimum time width.
9.2.2
Data Ready Output Signal Restart
The Data Ready output signal restarts on the DRRB command’s rising edge, on the ECL logical high
level (–0.8V).
DRRB may also be grounded, or may float, for normal free-running of the Data Ready output signal. The
Data Ready signal’s restart sequence depends on the logical level of the external encoding clock, at a
DRRB rising edge instant:
The DRRB’s rising edge occurs when the external encoding clock input (CLK/CLKB) is LOW : the
Data Ready output’s first rising edge occurs after half a clock period on the clock’s falling edge, and a
TDR delay time of 410 ps, as defined above.
The DRRB’s rising edge occurs when the external encoding clock input (CLK/CLKB) is HIGH : the
Data Ready output’s first rising edge occurs after one clock period on the clock’s falling edge, and a
TDR delay time of 410 ps.
Consequently, as the analog input is sampled on the clock’s rising edge, the first digitized data corre-
sponding to the first acquisition (N), after a Data Ready signal restart (rising edge), is always strobed by
the third rising edge of the Data Ready signal.
The time delay (TD1) is specified between the last point of a change in the differential output data (zero
crossing point) to the rising or falling edge of the differential Data Ready signal (DR/DRB) [zero crossing
point].
Note:
For normal initialization of the Data Ready output signal, the external encoding clock signal frequency and
level must be controlled. The minimum encoding clock sampling rate for the ADC is 150 Msps, due to the
internal Sample and Hold drop rate. Consequently the clock cannot be stopped.
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相關(guān)代理商/技術(shù)參數(shù)
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