參數(shù)資料
型號(hào): TRF2050PW
廠商: TEXAS INSTRUMENTS INC
元件分類(lèi): PLL合成/DDS/VCOs
英文描述: PLL FREQUENCY SYNTHESIZER, 1200 MHz, PDSO20
封裝: PLASTIC, SO-20
文件頁(yè)數(shù): 26/34頁(yè)
文件大?。?/td> 543K
代理商: TRF2050PW
TRF2050
LOW-VOLTAGE 1.2-GHz FRACTIONAL-N/INTEGER-N SYNTHESIZER
SLWS030E– JUNE 1996 – REVISED OCTOBER 2000
32
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
test modes
The LOCK terminal may be used for test operations by terminating pin 19 to ground. When test modes are
enabled, the LOCK terminal is connected to internal nodes of the TRF2050. Test modes are enabled by writing
ones to the two LSBs of the E-Word. Test modes are disabled by terminating pin 19 to VCC through a pull-up
resistor of 10 k
.
Table 10. Test Modes
T1
T0
MODE
0
Buffered output of the fractional accumulator
0
1
Buffered output of the auxiliary divider
1
0
Buffered output of the main divider
1
Buffered output of the reference divider
The test mode can be used to verify the division ratio of the reference divider, the auxiliary divider, and the main
divider and prescaler.
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