參數(shù)資料
型號: TRF2050PW
廠商: TEXAS INSTRUMENTS INC
元件分類: PLL合成/DDS/VCOs
英文描述: PLL FREQUENCY SYNTHESIZER, 1200 MHz, PDSO20
封裝: PLASTIC, SO-20
文件頁數(shù): 16/34頁
文件大?。?/td> 543K
代理商: TRF2050PW
TRF2050
LOW-VOLTAGE 1.2-GHz FRACTIONAL-N/INTEGER-N SYNTHESIZER
SLWS030E– JUNE 1996 – REVISED OCTOBER 2000
23
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
main divider – SA7025 emulation (continued)
For contiguous channels, the following rules must be observed:
For PR = 01: 61
≤ NM1 ≤ 4095 and 0 ≤ NM2 ≤ 63, which yields minimum and maximum divide ratios of 4032
and 266303, respectively.
For PR = 10: 14
≤ NM1 ≤ 4095 and 0 ≤ NM2 ≤ 15, and 0 ≤ NM3 ≤ 15, which yields minimum and maximum
divide ratios of 1096 and 264335, respectively.
main divider – synchronization
The A-Word is loaded only when a main divider synchronization signal is active. This prevents phase jumps
when reprogramming the main divider. The synchronization signal is generated by the main divider, and it is
active while the main divider is counting down from the programmed value. When the main divider reaches its
terminal count, a main divider output pulse is sent to the main phase detector. Also at this time, the loading of
the A-Word is disabled. Therefore, to correctly load the new A-Word, the STROBE signal must be active high
for at least a minimum number of VCO input cycles at RFIN.
main divider – fractional accumulator
The TRF2050 main synthesizer loop can operate as a traditional integer-N feedback PLL or as a fractional-N
feedback PLL. The integer-N feedback loop divides the VCO frequency by integer values of N, which results
in phase detector reference comparisons at the desired channel spacing. A fractional-N feedback loop divides
the VCO frequency by an integer term plus a fractional term, which results in phase detector reference
comparisons at integer multiples of the desired system channel spacing.
Integer-N division: VCO frequency