參數(shù)資料
型號(hào)： TRCV0110G
廠商： Lineage Power
英文描述： 10 Gbits/s Clock Recovery, 1:16 Data Multiplexer(10 G位/秒時(shí)鐘恢復(fù)，1:16數(shù)據(jù)多路復(fù)用器)
中文描述： 10 Gb /秒時(shí)鐘恢復(fù)，1:16數(shù)據(jù)復(fù)用器（10政位/秒時(shí)鐘恢復(fù)，1:16數(shù)據(jù)多路復(fù)用器）
文件頁(yè)數(shù)： 21/24頁(yè)
文件大小： 524K
代理商： TRCV0110G
Advance Data Sheet
August 2000
TRCV0110G
10 Gbits/s Clock Recovery, 1:16 Data Demultiplexer
21
Lucent Technologies Inc.
Timing Characteristics
Note that all timing diagrams involving differential signals represent the positive signal as a solid line and the neg-
ative signal as a dashed line. This is especially important when referencing the rising or falling edge of a differential
signal.
Output Timing
The timing relationships between the output 622 MHz clock CK622P/N and the output demultiplexer data
D[15:0]P/N are shown in Figure 8.
0367(F)r.1
Figure 8. Transmit Timing Waveform with 622 MHz Clock
The output 622 MHz clock and data signals from Figure 8 are characterized in Table 17.
Table 17. LVDS Output Pin ac Timing Characteristics
Applicable
Pins
CKOP/N
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
—
Duty Cycle
All signals
differential
FREQCKO = 0
FREQCKO = 1
All signals
differential
40
50
60
%
t
PERIOD
CKOP/N Clock Period
—
—
40
—
TBD
1.6
6.4
50
1.6
0.8
—
—
60
—
TBD
ns
ns
%
ns
ns
CK622P/N
—
Duty Cycle
t
PERIOD
t
DD1
CK622P/N Clock Period
Time Delay from Clock Edge
to D[15:0]P/N Leading Edge
Time Delay from Clock Edge
to D[15:0]P/N Trailing Edge
Rise, Fall Times:
20%—80%
Transition Skew Rise to Fall
D[15:0]P/N,
CK622P/N
t
DD2
TBD
0.8
TBD
ns
t
RISE
,
t
FALL
t
SKEW
TBD
TBD
TBD
ps
–
TBD
0
TBD
ps
CK622P/N
D[15:0]P/N
OUTPUTS
OUTPUT
DATA 1
DATA 2
tDD1
tDD2
tPERIOD
DATA 3
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