參數(shù)資料
型號(hào)： TRCV0110G
廠商： Lineage Power
英文描述： 10 Gbits/s Clock Recovery, 1:16 Data Multiplexer(10 G位/秒時(shí)鐘恢復(fù)，1:16數(shù)據(jù)多路復(fù)用器)
中文描述： 10 Gb /秒時(shí)鐘恢復(fù)，1:16數(shù)據(jù)復(fù)用器（10政位/秒時(shí)鐘恢復(fù)，1:16數(shù)據(jù)多路復(fù)用器）
文件頁(yè)數(shù)： 2/24頁(yè)
文件大小： 524K
代理商： TRCV0110G
TRCV0110G
10 Gbits/s Clock Recovery, 1:16 Data Demultiplexer
Advance Data Sheet
August 2000
2
Lucent Technologies Inc.
Table of Contents
Contents
Page
Features ...................................................................................................................................................................1
Applications ..............................................................................................................................................................1
Description ................................................................................................................................................................1
Pin Information .........................................................................................................................................................4
Functional Overview ...............................................................................................................................................11
FEC Rate Support ..................................................................................................................................................11
Clock and Data Recovery (CDR) ............................................................................................................................11
Data Input Circuit .................................................................................................................................................11
Clock Recovery Operation ...................................................................................................................................12
Clock Recovery PLL Loop Filter ..........................................................................................................................12
CDR Acquisition Time ..........................................................................................................................................13
CDR Generated Jitter ..........................................................................................................................................13
CDR Input Jitter Tolerance ..................................................................................................................................13
Data Path Configuration Option (ENLBDN) .........................................................................................................13
Loss of Lock (LCKLOSSN) ..................................................................................................................................13
Clock Recovery Jitter Tolerance and Jitter Transfer Specifications .....................................................................14
Reference Frequency (REFCLKP/N, REFFREQ) (Standard SONET Rate) ........................................................15
Reference Frequency (REFCLKP/N, REFFREQ) (FEC Rate) ............................................................................15
Demultiplexer Operation .........................................................................................................................................16
Demultiplexer Data Mute (MUTEDMXN) .............................................................................................................16
CK622P/N Output Mute (MUTE622N) .................................................................................................................16
CKOP/N Output Frequency Select (FREQCKO) .................................................................................................16
CKOP/N Output Mute (MUTECKON) ..................................................................................................................16
Reset (RESETN) ..................................................................................................................................................16
Absolute Maximum Ratings ....................................................................................................................................17
Handling Precautions .............................................................................................................................................17
Operating Conditions ..............................................................................................................................................17
Electrical Characteristics ........................................................................................................................................18
LVDS, CMOS, and CML Input Pins .....................................................................................................................18
Timing Characteristics ............................................................................................................................................21
Output Timing ......................................................................................................................................................21
Outline Diagram ......................................................................................................................................................22
177-Pin BGA ........................................................................................................................................................22
Ordering Information ...............................................................................................................................................23
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