參數(shù)資料
型號(hào)： TRCV0110G
廠商： Lineage Power
英文描述： 10 Gbits/s Clock Recovery, 1:16 Data Multiplexer(10 G位/秒時(shí)鐘恢復(fù)，1:16數(shù)據(jù)多路復(fù)用器)
中文描述： 10 Gb /秒時(shí)鐘恢復(fù)，1:16數(shù)據(jù)復(fù)用器（10政位/秒時(shí)鐘恢復(fù)，1:16數(shù)據(jù)多路復(fù)用器）
文件頁(yè)數(shù)： 13/24頁(yè)
文件大?。?/td> 524K
代理商： TRCV0110G
Advance Data Sheet
August 2000
TRCV0110G
10 Gbits/s Clock Recovery, 1:16 Data Demultiplexer
13
Lucent Technologies Inc.
Clock and Data Recovery (CDR)
(continued)
CDR Acquisition Time
The CDR will acquire phase/frequency lock within 10 ms after powerup and a valid SONET signal or a 2
23
– 1
PRBS data signal is applied.
CDR Generated Jitter
The CDR’s generated jitter performance meets the requirements shown in Table 7. These specifications apply to
the jitter generated at the 622 MHz recovered clock pin CK622P/N when no jitter is present on the input and the
data sequence is a valid OC-192/STM-64 SONET/SDH signal.
Table 7. Clock and Data Recovery Generated Jitter Specifications
* When the loop filter in Table 6 and Figure 4 is used.
CDR Input Jitter Tolerance
The CDR’s jitter tolerance performance meets the requirement shown in Figure 5 when the loop filter in Figure 4 is
used, and the data sequence is a valid OC-192/STM-64 SONET/SDH signal.
Data Path Configuration Option (ENLBDN)
Either the primary CML logic level input DATAP/N or a secondary CML logic level input LBDP/N can be selected as
the source of the 10 Gbits/s data signal. The LBDP/N input can be used as a system loopback path when
DATAP/N is the normal data path.
Loss of Lock (LCKLOSSN)
The LCKLOSSN signal is asserted low when the frequency of the CDR PLL’s VCO deviates ±600 ppm from the
frequency reference set by the REFCLK. Activation of LCKLOSSN is guaranteed to be within
TBD
μ
s from the time
that the VCO frequency drifts outside the ±600 ppm error band. LCKLOSSN is deactivated
TBD
μ
s after the PLL’s
VCO frequency is within ±600 ppm of the reference set by the REFCLK.
Note that when the optical or loopback data input is removed, the clock and data recovery VCO will drift to within
±600 ppm of the REFCLK frequency. Under these conditions, the comparison of the VCO frequency to the
REFCLK frequency is not a reliable indicator of whether the CDR is actually locked to the data or not. To create a
more reliable indicator of loss of lock, internal logic detects a stuck at logic high or stuck at logic low condition on
the input data and forces the LCKLOSSN signal to declare an out of lock condition when there are no data
transitions, regardless of the frequency of the VCO relative to REFCLK. Note however, that and ac-coupled input
may still drift to a differential voltage near zero and random transitions may occur due to noise. Under these
conditions, the LCKLOSSN signal may falsely declare in lock even though no data timing is present.
Parameter
Typical
Max
(Device)
*
TBD
Unit
Generated Jitter (p-p) SONET Rate:
Measured with 50 kHz to 80 MHz Bandpass Filter
1 UI = 1/9.95328 GHz
Generated Jitter (p-p) FEC Rate:
Measured with
kHz to
MHz Bandpass Filter
1 UI = (14/15)(9.95328 GHz)
TBD
UIp-p
TBD
TBD
UIp-p
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