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| 型號(hào)： | TPS65910RSLT |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 電源管理 |
| 英文描述： | POWER SUPPLY SUPPORT CKT, PQCC48 |
| 封裝： | 6 X 6 MM, 0.40 MM PITCH, GREEN, PLASTIC, VQFN-48 |
| 文件頁(yè)數(shù)： | 77/86頁(yè) |
| 文件大?。?/td> | 534K |
| 代理商： | TPS65910RSLT |
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PRODUCTPREVIEW
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SWCS046A – MARCH 2010 – REVISED MAY 2010
Bits
Field Name
Description
Type
Reset
0
VMBDCH_IT
VBAT > VMBDCH event interrupt status.
RW
0
Active only if Main Battery comparator VMBCH programmable threshold
W1 to Clr
is not bypassed (VMBCH_SEL[1:0]
≠ 00)
Table 71. INT_MSK_REG
Address Offset
0x51
Physical Address
Instance
Description
Interrupt mask register:
When *_IT_MSK is set to 1, the associated interrupt is masked: INT1 signal is not activated, but *_IT
interrupt status bit is updated.
When *_IT_MSK is set to 0, the associated interrupt is enabled: INT1 signal is activated, *_IT is
updated.
Type
RW
7
6
5
4
3
2
1
0
VMBHI_IT_MSK
HOTDIE_IT_MSK
PWRON_IT_MSK
VMBDCH_IT_MSK
PWRHOLD_IT_MSK
PWRON_LP_IT_MSK
RTC_ALARM_IT_MSK
RTC_PERIOD_IT_MSK
Bits
Field Name
Description
Type
Reset
7
RTC_PERIOD_IT_MS RTC period event interrupt mask.
RW
0
K
6
RTC_ALARM_IT_MS
RTC alarm event interrupt mask.
RW
0
K
5
HOTDIE_IT_MSK
Hot die event interrupt mask.
RW
0
4
PWRHOLD_IT_MSK
PWRHOLD rising edge event interrupt mask.
RW
0
3
PWRON_LP_IT_MSK
PWRON Long Press event interrupt mask.
RW
0
2
PWRON_IT_MSK
PWRON event interrupt mask.
RW
0
1
VMBHI_IT_MSK
VBAT > VMBHI event interrupt mask.
RW
1
When 0, enable the device automatic switch on at BACKUP to OFF or
NOSUPPLY to OFF device state transition (EEPROM bit)
0
VMBDCH_IT_MSK
Setting supply state control though EN3 signal
RW
0
Table 72. INT_STS2_REG
Address Offset
0x52
Physical Address
Instance
Description
Interrupt status register:
The interrupt status bit is set to 1 when the associated interrupt event is detected. Interrupt status bit is
cleared by writing 1.
Type
RW
7
6
5
4
3
2
1
0
Reserved
GPIO0_F_IT
GPIO0_R_IT
Bits
Field Name
Description
Type
Reset
7:2
Reserved
Reserved bit
RW
0
W1 to Clr
1
GPIO0_F_IT
GPIO0 falling edge detection interrupt status
RW
0
W1 to Clr
Copyright 2010, Texas Instruments Incorporated
79
Product Folder Link(s): TPS65910
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