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| 型號： | TPS65910RSLT |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 電源管理 |
| 英文描述： | POWER SUPPLY SUPPORT CKT, PQCC48 |
| 封裝： | 6 X 6 MM, 0.40 MM PITCH, GREEN, PLASTIC, VQFN-48 |
| 文件頁數(shù)： | 68/86頁 |
| 文件大?。?/td> | 534K |
| 代理商： | TPS65910RSLT |
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PRODUCTPREVIEW
SWCS046A – MARCH 2010 – REVISED MAY 2010
www.ti.com
7
6
5
4
3
2
1
0
Reserved
VDD2_PSKIP
VDD1_PSKIP
VIO_PSKIP
DCDCCKEXT
DCDCCKSYNC
Bits
Field Name
Description
Type
Reset
7:6
Reserved
Reserved bit
RO
0x0
R returns
0s
5
VDD2_PSKIP
VDD2 pulse skip mode enable (EEPROM bit)
RW
1
4
VDD1_PSKIP
VDD1 pulse skip mode enable (EEPROM bit)
RW
1
3
VIO_PSKIP
VIO pulse skip mode enable (EEPROM bit)
RW
1
2
DCDCCKEXT
This signal control the muxing of the GPIO0 pad:
RW
0
When 0: this pad is a GPIO
When 1: this pad is used as input for an external clock used for the
synchronisation of the DCDCs
1:0
DCDCCKSYNC
DCDC clock configuration:
RW
0x3
DCDCCKSYNC[1:0] = 00 : no synchronization of DCDC clocks
DCDCCKSYNC[1:0] = 01 : DCDC synchronous clock
DCDCCKSYNC[1:0] = 10 : no synchronization of DCDC clocks
DCDCCKSYNC[1:0] = 11 : DCDC synchronous clock with phase shift
Table 58. DEVCTRL_REG
Address Offset
0x3F
Physical Address
Instance
Description
Device control register
Type
RW
7
6
5
4
3
2
1
0
Reserved
RTC_PWDN
CK32K_CTRL
DEV_ON
DEV_SLP
DEV_OFF
DEV_OFF_RST
SR_CTL_I2C_SEL
Bits
Field Name
Description
Type
Reset
7
Reserved
Reserved bit
RO
0
R returns
0s
6
RTC_PWDN
When 1, disable the RTC digital domain (clock gating and reset of RTC
RW
1
registers and logic).
This register bit is not reset in BACKUP state. (EEPROM bit)
5
CK32K_CTRL
Internal 32-kHz clock source control bit (EEPROM bit):
RW
0
when 0, the internal 32-kHz clock source is the crystal oscillator or an
external 32-kHz clock in case the crystal oscillator is used in bypass
mode
when 1, the internal 32-kHz clock source is the RC oscillator.
4
SR_CTL_I2C_SEL
Smartreflex registers access control bit:
RW
0
when 0: access to smartreflex registers by smartreflex I2C
when 1: access to smartreflex registers by control I2C The smartreflex
registers are: VDD1_OP_REG, VDD1_SR_REG, VDD2_OP_REG and
VDD2_SR_REG.
3
DEV_OFF_RST
Write 1 will start an ACTIVE to OFF or SLEEP to OFF device state
RW
0
transition (switch-off event) and activate reset of the digital core.
2
DEV_ON
Write 1 will maintain the device on (ACTIVE or SLEEP device state) (if
RW
0
DEV_OFF = 0 and DEV_OFF_RST = 0).
70
Copyright 2010, Texas Instruments Incorporated
Product Folder Link(s): TPS65910
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