參數(shù)資料
型號: TPS65910RSLT
廠商: TEXAS INSTRUMENTS INC
元件分類: 電源管理
英文描述: POWER SUPPLY SUPPORT CKT, PQCC48
封裝: 6 X 6 MM, 0.40 MM PITCH, GREEN, PLASTIC, VQFN-48
文件頁數(shù): 26/86頁
文件大?。?/td> 534K
代理商: TPS65910RSLT
PRODUCTPREVIEW
1.2 V
SCLSR_EN2
PFM (pulse
skipping) mode
SW1
VDD1/VFB1
0.8 V
PFM (pulse
skipping) mode
PFM (pulse skipping) mode
PWM mode
T
dDVSEN
T
dDVSENL
T
dDVSEN
TSTEP[2:0]=001
TSTEP[2:0]=011
T
dDVSENL
SWCS046-021
SWCS046A – MARCH 2010 – REVISED MAY 2010
www.ti.com
Table 5. Supplies State Control Though SCLSR_EN1 and SCLSR_EN2 Timing Characteristics
Parameter
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tdEN: NREPSWON to supply state
change delay, SCLSR_EN1 or
0
ms
SCLSR_EN2 driven
tdEN: SCLSR_EN1 or
SCLSR_EN2 edge to supply state
1 × tCK32k = 31
s
change delay
tdVDDEN: SCLSR_EN1 or
SCLSR_EN2 edge to VDD1 or
3 × tCK32k = 63
s
VDD2 dc-dc turn on delay
Figure 9. VDD1 Supply Voltage Control Though SCLSR_EN1
NOTE
Register setting: VDD1_EN1 = 1, SEL[6:0] = hex13 in VDD1_SR_REG
Table 6. VDD1 Supply Voltage Control Through SCLSR_EN1 Timing Characteristics
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tdDVSEN: SCLSR_EN1 or SCLSR_EN2 edge to
2 × tCK32k = 62
s
VDD1 or VDD2 voltage change delay
tdDVSENL: VDD1 or VDD2 voltage settling delay
TSTEP[2:0] = 001
32
s
TSTEP[2:0] = 011 (default)
0.4/7.5 = 53
TSTEP[2:0] = 111
160
32
Copyright 2010, Texas Instruments Incorporated
Product Folder Link(s): TPS65910
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