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| 型號： | TPS65910RSLT |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 電源管理 |
| 英文描述： | POWER SUPPLY SUPPORT CKT, PQCC48 |
| 封裝： | 6 X 6 MM, 0.40 MM PITCH, GREEN, PLASTIC, VQFN-48 |
| 文件頁數(shù)： | 75/86頁 |
| 文件大?。?/td> | 534K |
| 代理商： | TPS65910RSLT |
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PRODUCTPREVIEW
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SWCS046A – MARCH 2010 – REVISED MAY 2010
Bits
Field Name
Description
Type
Reset
7:5
RSVD
Reserved bit
RO
0x0
R returns
0s
4
SPARE_EN2
Spare bit
RW
0
3
VDD3_EN2
When 1:
RW
0
When SDASR_EN2 is high the supply is on.
When SDASR_EN2 is low and SLEEP_KEEP_RES_ON = 0 the supply
voltage is off.
When SDASR_EN2 is low and SLEEP_KEEP_RES_ON = 1 the SMPS
is working in low power mode.
When control bit = 0 no effect: supply state is driven though registers
programming and the device state
2
VDD2_EN2
When control bit = 1:
RW
0
When SDASR_EN2 is high the supply voltage is programmed though
VDD2_OP_REG register, and it can also be programmed off.
When SDASR_EN2 is low the supply voltage is programmed though
VDD2_SR_REG register, and it can also be programmed off.
When SDASR_EN2 is low and and VDD2_KEEPON = 1 the SMPS is
working in low power mode, if not tuned off though VDD2_SR_REG
register.
When control bit = 0 no effect: supply state is driven though registers
programming and the device state
1
VDD1_EN2
When control bit = 1:
RW
0
When SDASR_EN2 is high the supply voltage is programmed though
VDD1_OP_REG register, and it can also be programmed off.
When SDASR_EN2 is low the supply voltage is programmed though
VDD1_SR_REG register, and it can also be programmed off.
When SDASR_EN2 is low and and VDD1_KEEPON = 1 the SMPS is
working in low power mode, if not tuned off though VDD1_SR_REG
register.
When control bit = 0 no effect: supply state is driven though registers
programming and the device state
0
VIO_EN2
When control bit = 1,
RW
0
supply state is driven by the SCLSR_EN2 control signal and is also
defined though SLEEP_KEEP_RES_ON register setting:
When SDASR _EN2 is high the supply is on,
When SDASR _EN2 is low :
- the supply is off (default) or the SMPS is working in low power mode if
VIO_KEEPON = 1
When control bit = 0 no effect: SMPS state is driven though registers
programming and the device state
Table 68. EN3_LDO_ASS_REG
Address Offset
0x49
Physical Address
Instance
Description
Configuration Register setting the LDO regulators, driven by the EN3 signal.
When control bit = 1, LDO regulator state is driven by the EN3 control signal and is also defined though
SLEEP_KEEP_LDO_ON register setting:
When EN3 is high the regulator is on,
When EN3 is low:
- the regulator is off if its corresponding Control bit = 0 in SLEEP_KEEP_LDO_ON register
- the regulator is working in low power mode if its corresponding control bit = 1 in
SLEEP_KEEP_LDO_ON register
When control bit = 0 no effect: LDO regulator state is driven though registers programming and the
device state.
Type
RW
7
6
5
4
3
2
1
0
VDAC_EN3
VPLL_EN3
VAUX33_EN3
VAUX2_EN3
VAUX1_EN3
VDIG2_EN3
VDIG1_EN3
VMMC_EN3
Copyright 2010, Texas Instruments Incorporated
77
Product Folder Link(s): TPS65910
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