參數(shù)資料
型號(hào): TPS65023QRSBRQ1
廠商: TEXAS INSTRUMENTS INC
元件分類(lèi): 電源管理
英文描述: POWER SUPPLY SUPPORT CKT, PQCC40
封裝: 5 X 5 MM, GREEN, PLASTIC, WQFN-40
文件頁(yè)數(shù): 29/54頁(yè)
文件大?。?/td> 1546K
代理商: TPS65023QRSBRQ1
www.ti.com
SLVS927C – MARCH 2009 – REVISED MAY 2010
CON_CTRL2. Register Address: 05h (read/write)
Default Value: 40h
CON_CTRL2
B7
B6
B5
B4
B3
B2
B1
B0
Bit name and
Core adj
DCDC2
DCDC1
DCDC3
GO
function
allowed
discharge
Default
0
1
0
Default value
UVLO +
RESET(1)
UVLO
loaded by:
DONE
Read/Write
R/W
The CON_CTRL2 register can be used to take control the inductive converters.
RESET(1): CON_CTRL2[6] is reset to its default value by one of these events:
undervoltage lockout (UVLO)
HOT_RESET pulled low
RESPWRON active
VRTC below threshold
Bit 7
GO
0 =
no change in the output voltage for the DCDC1 converter
1 =
the output voltage of the DCDC1 converter is changed to the value defined in DEFCORE with
the slew rate defined in DEFSLEW. This bit is automatically cleared when the DVM transition is
complete. The transition is considered complete in this case when the desired output voltage
code has been reached, not when the VDCDC3 output voltage is actually in regulation at the
desired voltage.
Bit 6
CORE ADJ allowed
0 =
the output voltage is set with the I2C register
1 =
DEFDCDC1 is either connected to GND or VCC or an external voltage divider. When
connected to GND or VCC, VDCDC1 defaults to 1.2 V or 1.6 V respectively at start-up.
Bit 2–0
0 =
the output capacitor of the associated converter is not actively discharged when the converter is
disabled
1 =
the output capacitor of the associated converter is actively discharged when the converter is
disabled. This decreases the fall time of the output voltage at light load.
Copyright 2009–2010, Texas Instruments Incorporated
35
Product Folder Link(s): TPS65023-Q1
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