參數(shù)資料
型號(hào): TPS65023QRSBRQ1
廠商: TEXAS INSTRUMENTS INC
元件分類: 電源管理
英文描述: POWER SUPPLY SUPPORT CKT, PQCC40
封裝: 5 X 5 MM, GREEN, PLASTIC, WQFN-40
文件頁(yè)數(shù): 28/54頁(yè)
文件大小: 1546K
代理商: TPS65023QRSBRQ1
SLVS927C – MARCH 2009 – REVISED MAY 2010
www.ti.com
CON_CTRL. Register Address: 04h (read/write)
Default Value: B1h
CON_CTRL
B7
B6
B5
B4
B3
B2
B1
B0
Bit name and
DCDC2
DCDC3
LOW
FPWM
function
PHASE1
PHASE0
PHASE1
PHASE0
RIPPLE
DCDC2
DCDC1
DCDC3
Default
1
0
1
0
Default value
UVLO
loaded by:
Read/Write
R/W
The CON_CTRL register is used to force any or all of the converters into forced PWM operation, when low
output voltage ripple is vital. It is also used to control the phase shift between the three converters in order to
minimize the input RMS current, hence reduce the required input blocking capacitance. The DCDC1 converter is
taken as the reference and consequently has a fixed zero phase shift.
DCDC2 CONVERTER
DCDC3 CONVERTER
CON_CTRL<7:6>
CON_CTRL<5:4>
DELAYED BY
00
zero
00
zero
01
1/4 cycle
01
1/4 cycle
10
1/2 cycle
10
1/2 cycle
11
3/4 cycle
11
3/4 cycle
Bit 3
LOW RIPPLE:
0 =
PFM mode operation optimized for high efficiency for all converters
1 =
PFM mode operation optimized for low output voltage ripple for all converters
Bit 2
FPWM DCDC2:
0 =
DCDC2 converter operates in PWM / PFM mode
1 =
DCDC2 converter is forced into fixed frequency PWM mode
Bit 1
FPWM DCDC1:
0 =
DCDC1 converter operates in PWM / PFM mode
1 =
DCDC1 converter is forced into fixed frequency PWM mode
Bit 0
FPWM DCDC3:
0 =
DCDC3 converter operates in PWM / PFM mode
1 =
DCDC3 converter is forced into fixed frequency PWM mode
34
Copyright 2009–2010, Texas Instruments Incorporated
Product Folder Link(s): TPS65023-Q1
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