參數(shù)資料
型號(hào)： TPS65023QRSBRQ1
廠商： TEXAS INSTRUMENTS INC
元件分類： 電源管理
英文描述： POWER SUPPLY SUPPORT CKT, PQCC40
封裝： 5 X 5 MM, GREEN, PLASTIC, WQFN-40
文件頁(yè)數(shù)： 27/54頁(yè)
文件大?。?/td> 1546K
代理商： TPS65023QRSBRQ1
www.ti.com
SLVS927C – MARCH 2009 – REVISED MAY 2010
MASK. Register Address: 02h (read/write)
Default Value: C0h
MASK
B7
B6
B5
B4
B3
B2
B1
B0
Bit name and
MASK
function
PWRFAILZ
LOWBATTZ
VDCDC1
VDCDC2
VDCDC3
LDO2
LDO1
Default
1
0
Default value
UVLO
loaded by:
Read/Write
R/W
The MASK register can be used to mask particular fault conditions from appearing at the INT pin. MASK<n> = 1
masks PGOODZ<n>.
REG_CTRL. Register Address: 03h (read/write)
Default Value: FFh
The REG_CTRL register is used to disable or enable the power supplies via the serial interface. The contents of
the register are logically AND’ed with the enable pins to determine the state of the supplies. A UVLO condition
resets the REG_CTRL to 0xFF, so the state of the supplies defaults to the state of the enable pin. The
REG_CTRL bits are automatically reset to default when the corresponding enable pin is low.
REG_CTRL
B7
B6
B5
B4
B3
B2
B1
B0
Bit name and
VDCDC1
VDCDC2
VDCDC3
LDO2
LDO1
function
ENABLE
Default
1
Set by signal
DCDC1_ENZ DCDC2_ENZ DCDC3_ENZ
LDO_ENZ
Default value
UVLO
loaded by:
Read/Write
R/W
Bit 5
VDCDC1 ENABLE
DCDC1 Enable. This bit is logically AND’ed with the state of the DCDC1_EN pin to turn on the DCDC1
converter. Reset to 1 by a UVLO condition, the bit can be written to 0 or 1 via the serial interface. The
bit is reset to 1 when the pin DCDC1_EN is pulled to GND, allowing DCDC1 to turn on when
DCDC1_EN returns high.
Bit 4
VDCDC2 ENABLE
DCDC2 Enable. This bit is logically AND’ed with the state of the DCDC2_EN pin to turn on the DCDC2
converter. Reset to 1 by a UVLO condition, the bit can be written to 0 or 1 via the serial interface. The
bit is reset to 1 when the pin DCDC2_EN is pulled to GND, allowing DCDC2 to turn on when
DCDC2_EN returns high.
Bit 3
VDCDC3 ENABLE
DCDC3 Enable. This bit is logically AND’ed with the state of the DCDC3_EN pin to turn on the DCDC3
converter. Reset to 1 by a UVLO condition, the bit can be written to 0 or 1 via the serial interface. The
bit is reset to 1 when the pin DCDC3_EN is pulled to GND, allowing DCDC3 to turn on when
DCDC3_EN returns high.
Bit 2
LDO2 ENABLE
LDO2 Enable. This bit is logically AND’ed with the state of the LDO2_EN pin to turn on LDO2. Reset to
1 by a UVLO condition, the bit can be written to 0 or 1 via the serial interface. The bit is reset to 1 when
the pin LDO_EN is pulled to GND, allowing LDO2 to turn on when LDO_EN returns high.
Bit 1
LDO1 ENABLE
LDO1 Enable. This bit is logically AND’ed with the state of the LDO1_EN pin to turn on LDO1. Reset to
1 by a UVLO condition, the bit can be written to 0 or 1 via the serial interface. The bit is reset to 1 when
the pin LDO_EN is pulled to GND, allowing LDO1 to turn on when LDO_EN returns high.
Copyright 2009–2010, Texas Instruments Incorporated
33
Product Folder Link(s): TPS65023-Q1
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TPS65023RSBRG4 功能描述:電池管理 6Ch Pwr Mgmt IC RoHS:否 制造商:Texas Instruments 電池類型:Li-Ion 輸出電壓:5 V 輸出電流:4.5 A 工作電源電壓:3.9 V to 17 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:VQFN-24 封裝:Reel
TPS65023RSBT 功能描述:電池管理 6-Channel Power Management IC RoHS:否 制造商:Texas Instruments 電池類型:Li-Ion 輸出電壓:5 V 輸出電流:4.5 A 工作電源電壓:3.9 V to 17 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:VQFN-24 封裝:Reel
TPS65023RSBT 制造商:Texas Instruments 功能描述:Power Management IC
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