參數(shù)資料
型號： TPS59116RGER
廠商： TEXAS INSTRUMENTS INC
元件分類： 穩(wěn)壓器
英文描述： SWITCHING CONTROLLER, PQCC24
封裝： 4 X 4 MM, GREEN, PLASTIC, VQFN-24
文件頁數(shù)： 9/36頁
文件大?。?/td> 827K
代理商： TPS59116RGER
f
z1 +
1
2p
C
R
C
+
f
0
10
R1 +
V
OUT * 0.75
0.75
R2
f
0 +
1
2p
ESR
C
O
v
f
SW
3
TI Information — Selective Disclosure
www.ti.com
SLUSA57 – NOVEMBER 2010
6. Calculate CC. The purpose of CC is to reduce the DC component to obtain high DC feedback gain. However,
as it causes phase delay, another zero is needed to cancel this effect. This zero, wz1, is determined by CC
and RC. It is recommended that wz1 be 10 times lower than the f0 frequency.
(22)
7. When using adjustable mode, determine the value of R1 and R2. .
(23)
D-CAP Mode Operation
A buck converter system using D-CAP Mode can be simplified as below.
Figure 3. Linearizing the Modulator
The VDDQSNS voltage is compared to the internal reference voltage after divider resistors. The PWM
comparator determines the time to turn-on the top MOSFET. The gain and speed of the comparator is high
enough to keep the voltage at the beginning of each on cycle (or the end of each off cycle) substantially
constant. The DC output voltage may have line regulation due to ripple amplitude that slightly increases as the
input voltage increase.
For loop stability, the 0-dB frequency, f0, defined in Equation 24 needs to be lower than 1/3 of the switching
frequency.
(24)
As f0 is determined solely by the output capacitor characteristics, loop stability of D-CAP mode is determined
by the capacitor chemistry. For example, specialty polymer capacitors (SP-CAP) have CO in the order of several
100 mF and have an ESR in the range of 10 m. This makes f0 on the order of 100 kHz or less and the loop is
then stable. However, ceramic capacitors have an f0 of more than 700 kHz, which is not suitable for this
operational mode.
Although D-CAP mode provides many advantages such as ease-of-use, minimum external components
configuration and extremely short response time, because there is no error amplifier in the loop, a sufficient
amount of feedback signal needs to be provided by an external circuit to reduce jitter level.
The required signal level is approximately 15 mV at the comparing point. This gives VRIPPLE = (VOUT/0.75) x 15
(mV) at the output node. The output capacitor ESR should meet this requirement.
Copyright 2010, Texas Instruments Incorporated
17
Product Folder Link(s): TPS59116
相關(guān)PDF資料
PDF描述
TRU050-GACFA17.920-8.960 PHASE LOCKED LOOP, CDSO16
TRU050-GACFA41.2416-20.6208 PHASE LOCKED LOOP, CDSO16
TRU050-GACGA16.896-8.448 PHASE LOCKED LOOP, CDSO16
TRU050-GACHA13.824-6.912 PHASE LOCKED LOOP, CDSO16
TRU050-GALGA47.457-23.7285 PHASE LOCKED LOOP, CDSO16
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