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參數資料
| 型號： | TP5510N |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Full Duplex Analog Front End for Consumer Applications |
| 中文描述： | 全雙工模擬前端的消費應用 |
| 文件頁數： | 6/12頁 |
| 文件大小： | 197K |
| 代理商： | TP5510N |
Timing Specifications
Unless otherwise noted, limits printed in
BOLD
characters are guaranteed for V
CC
e
5.0V
g
5%, V
BB
e b
5.0V
g
5%; T
A
e
0
§
C to 70
§
C by correlation with 100% electrical testing at T
A
e
25
§
C. All other limits are
assured by correlation with other production tests and/or product design and characterization. All signals referenced to GNDA.
Typicals specified at V
CC
e
5.0V, V
BB
e b
5.0V, T
A
e
25
§
C. All timing parameters are measured at V
OH
e
2.0V and V
OL
e
0.7V. See Definitions and Timing Conventions section for test methods information.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
1/t
PM
Frequency of Master Clocks
Depends on the Device Used and the
BCLK
D
/CLKSEL Pin.
MCLK
E
and MCLK
D
MCLK
E
and MCLK
D
MCLK
E
and MCLK
D
1.536
1.544
2.048
MHz
MHz
MHz
t
DM
t
FM
t
PB
t
DB
t
FB
t
WMH
t
WML
t
SBFM
Rise Time of Master Clock
50
ns
Fall Time of Master Clock
50
ns
Period of Bit Clock
485
488
15725
ns
Rise Time of Bit Clock
BCLK
E
and BCLK
D
BCLK
E
and BCLK
D
MCLK
E
and MCLK
D
MCLK
E
and MCLK
D
First Bit Clock after the Leading
Edge of FS
E
Long Frame Only
50
ns
Fall Time of Bit Clock
50
ns
Width of Master Clock High
160
ns
Width of Master Clock Low
160
ns
Set-Up Time from BCLK
E
High
to MCLK
E
Falling Edge
Set-Up Time from FS
E
High
to MCLK
E
Falling Edge
Width of Bit Clock High
100
ns
t
SFFM
100
ns
t
WBH
t
WBL
t
HBFL
V
IH
e
2.2V
V
IL
e
0.6V
Long Frame Only
160
ns
Width of Bit Clock Low
160
ns
Holding Time from Bit Clock
Low to Frame Sync
0
ns
t
HBFS
Holding Time from Bit Clock
High to Frame Sync
Short Frame Only
0
ns
t
SFB
Set-Up Time from Frame Sync
to Bit Clock Low
Long Frame Only
115
ns
t
DBD
Delay Time from BCLK
E
High
to Data Valid
Load
e
150 pF plus 2 LSTTL Loads
0
140
ns
t
DBTS
t
DZC
Delay Time to TS
E
Low
Delay Time from BCLK
E
Low to
Data Output Disabled
Load
e
150 pF plus 2 LSTTL Loads
C
L
e
0 pF to 150 pF
140
ns
50
165
ns
t
DZF
Delay Time to Valid Data from
FS
E
or BCLK
E
, Whichever
Comes Later
C
L
e
0 pF to 150 pF
20
165
ns
t
SDB
Set-Up Time from D
D
Valid to
BCLK
D/E
Low
Hold Time from BCLK
D/E
Low to
D
D
Invalid
Set-Up Time from FS
E/D
to
BCLK
E/D
Low
Hold Time from BCLK
E/D
Low
to FS
E/D
Low
Hold Time from 3rd Period of
Bit Clock Low to Frame Sync
(FS
E
or FS
D
)
Minimum Width of the Frame
Sync Pulse (Low Level)
50
ns
t
HBD
50
ns
t
SF
Short Frame Sync Pulse (1 Bit Clock
Period Long)
50
ns
t
HF
Short Frame Sync Pulse (1 Bit Clock
Period Long)
100
ns
t
HBFl
Long Frame Sync Pulse (from 3 to 8 Bit
Clock Periods Long)
100
ns
t
WFL
64k Bit/s Operating Mode
160
ns
http://www.national.com
6
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