參數(shù)資料
型號: TP5510N
廠商: National Semiconductor Corporation
英文描述: Full Duplex Analog Front End for Consumer Applications
中文描述: 全雙工模擬前端的消費應(yīng)用
文件頁數(shù): 4/12頁
文件大小: 197K
代理商: TP5510N
Functional Description
(Continued)
edges latch in the seven remaining bits. Both devices may
utilize the short frame sync pulse in synchronous or asyn-
chronous operating mode.
LONG FRAME SYNC OPERATION
To use the long frame mode, both the frame sync pulses,
FS
E
and FS
D
, must be three or more bit clock periods long,
with timing relationships specified inFigure 3. Based on the
transmit frame sync, FS
E
, the AFE will sense whether short
or long frame sync pulses are being used. For 64 kHz oper-
ation, the frame sync pulse must be kept low for a minimum
of 160 ns. The D
E
TRI-STATE output buffer is enabled with
the rising edge of FS
E
or the rising edge of BCLK
E
, which-
ever comes later, and the first bit clocked out is the sign bit.
The following seven BCLK
E
rising edges clock out the re-
maining seven bits. The D
E
output is disabled by the falling
BCLK
E
edge following the eighth rising edge, or by FS
E
going low, whichever comes later. A rising edge on the de-
code frame sync pulse, FS
D
, will cause the data at D
D
to be
latched in on the next eight falling edges of BCLK
D
(BCLK
E
in synchronous mode). Both devices may utilize the long
frame sync pulse in synchronous or asynchronous mode.
ENCODE SECTION
The encode section input is an operational amplifier with
provision for gain adjustment using two external resistors,
seeFigure 4. The low noise and wide bandwidth allow gains
in excess of 20 dB across the audio passband to be real-
ized. The op amp drives a unity-gain filter consisting of RC
active pre-filter, followed by an eighth order switched-ca-
pacitor bandpass filter clocked at 256 kHz. The output of
this filter directly drives the A/D sample-and-hold circuit.
The A/D is of compressing type according to
m
-law coding
conventions. A precision voltage reference is trimmed in
manufacturing to provide an input overload (t
MAX
) of nomi-
nally 2.5V peak (See Table of Transmission Characteris-
tics). The FS
E
frame sync pulse controls the sampling of the
filter output, and then the successive-approximation encod-
ing cycle begins. The 8-bit code is then loaded into a buffer
and shifted out through D
E
at the next FS
E
pulse. The total
encoding delay will be approximately 165
m
s (due to the
encode filter) plus 125
m
s (due to encoding delay), which
totals 290
m
s. Any offset voltage due to the filters or com-
parator is cancelled by sign bit integration.
DECODE SECTION
The decode section consists of an expanding DAC which
drives a fifth order switched-capacitor low pass filter
clocked at 256 kHz. The DAC is
m
-law and the 5th order low
pass filter corrects for the sin x/x attenuation due to the 8
kHz sample/hold. The filter is then followed by a 2nd order
RC active post-filter/power amplifier capable of driving a
600
X
load to a level of 7.2 dBm. The decode section is
unity-gain. Upon the occurrence of FS
D
, the data at the D
D
input is clocked in on the falling edge of the next eight
BCLK
D
(BCLK
E
) periods. At the end of the DAC time slot,
the D/A conversion cycle begins, and 10
m
s later the DAC
output is updated. The total DAC delay is
E
10
m
s (DAC
update) plus 110
m
s (filter delay) plus 62.5
m
s (
(/2
frame),
which gives approximately 180
m
s.
http://www.national.com
4
相關(guān)PDF資料
PDF描述
TP5510WM Full Duplex Analog Front End for Consumer Applications
TP6800 DIGITAL VIDEO CAMERA CONTROLLER
TP8452 PS/2 2D 3KEY MOUSE CONTROLLER
TP8472 PS/2 3D 3Key Mouse Controller
TP8472AM PS/2 3D 3Key Mouse Controller
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TP5510WM 制造商:Rochester Electronics LLC 功能描述:- Bulk
TP5510WMX 制造商:未知廠家 制造商全稱:未知廠家 功能描述:u-Law CODEC
TP5511N 制造商:未知廠家 制造商全稱:未知廠家 功能描述:A-Law CODEC
TP5511WM 制造商:未知廠家 制造商全稱:未知廠家 功能描述:A-Law CODEC
TP5512J 制造商:未知廠家 制造商全稱:未知廠家 功能描述:u-Law CODEC