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參數(shù)資料
| 型號： | TP5510N |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Full Duplex Analog Front End for Consumer Applications |
| 中文描述： | 全雙工模擬前端的消費(fèi)應(yīng)用 |
| 文件頁數(shù)： | 3/12頁 |
| 文件大小： | 197K |
| 代理商： | TP5510N |
Pin Description
(Continued)
Symbol
Function
MCLK
D
/PDN
Encode master clock. Must be 1.536 MHz,
1.544 MHz or 2.048 MHz. May be asyn-
chronous with MCLK
E
, but should be syn-
chronous with MCLK
E
for best perform-
ance. When MCLK
D
is connected continu-
ously low, MCLK
E
is selected for all inter-
nal timing. When MCLK
D
is connected
continuously high, the device is powered
down.
MCLK
E
Encode master clock. Must be 1.536 MHz,
1.544 MHz or 2.048 MHz. May be asyn-
chronous with MCLK
D
. Best performance
is realized from synchronous operation.
FS
E
Encode frame sync pulse input which en-
ables BCLK
E
to shift out the data on D
E
.
FS
E
is an 8 kHz pulse train, seeFigures 2
and 3 for timing details.
BCLK
E
The bit clock which shifts out the data on
D
E
. May vary from 64 kHz to 2.048 MHz,
but must be synchronous with MCLK
E
.
The TRI-STATE
é
data output which is en-
abled by FS
E
.
Open drain output which pulses low during
the A/D time slot.
D
E
TS
E
GS
E
Analog output of the encode input amplifi-
er. Used to externally set gain.
VF
E
I
b
Inverting input of the encode input amplifi-
er.
VF
E
I
a
Non-inverting input of the encode input
amplifier.
Functional Description
POWER-UP
When power is first applied, power-on reset circuitry initializ-
es the AFE and places it into a power-down state. All non-
essential circuits are deactivated and the D
E
and VF
D
O out-
puts are put in high impedance states. To power-up the de-
vice, a logical low level or clock must be applied to the
MCLK
D
/PDN pinand FS
E
and/or FS
D
pulses must be pres-
ent. Thus, 2 power-down control modes are available. The
first is to pull the MCLK
D
/PDN pin high; the alternative is to
hold both FS
E
and FS
D
inputs continuously lowDthe device
will power-down approximately 2 ms after the last FS
E
or
FS
D
pulse. Power-up will occur on the first FS
E
or FS
D
pulse. The TRI-STATE data output, D
E
, will remain in the
high impedance state until the second FS
E
pulse.
SYNCHRONOUS OPERATION
For synchronous operation, the same master clock and bit
clock should be used for both the encode and decode direc-
tions. In this mode, a clock must be applied to MCLK
E
and
the MCLK
D
/PDN pin can be used as a power-down control.
A low level on MCLK
D
/PDN powers up the device and a
high level powers down the device. In either case, MCLK
E
will be selected as the master clock for both the encode and
decode circuits. A bit clock must also be appliedtoBCLK
E
and the BCLK
D
/CLKSEL can be used to select the proper
internal divider for a master clock of 1.536 MHz, 1.544 MHz
or 2.048 MHz. For 1.544 MHz operation, the device auto-
matically compensates for the 193rd clock pulse each
frame.
With a fixed level on the BCLK
D
/CLKSEL pin, BCLK
E
will be
selected as the bit clock for both the encode and decode
directions. Table 1 indicates the frequencies of operation
which can be selected, depending on the state of BCLK
D
/
CLKSEL. In this synchronous mode, the bit clock, BCLK
E
,
may be from 64 kHz to 2.048 MHz, but must be synchro-
nous with MCLK
E
.
Each FS
E
pulse begins the encoding cycle and the data
from the previous encode cycle is shifted out of the enabled
D
E
output on the positive edge of BCLK
E
. After 8-bit clock
periods, the TRI-STATE D
E
output is returned to a high im-
pedance state. With an FS
D
pulse, data is latched via the
D
D
input on the negative edge of BCLK
E
(or BCLK
D
if run-
ning). FS
E
and FS
D
must be synchronous with MCLK
E/D
.
TABLE I. Selection of Master Clock Frequencies
BCLK
D
/CLKSEL
Master Clock
Frequency Selected
TP5510
Clocked
0
1
1.536 MHz or 1.544 MHz
2.048 MHz
1.536 MHz or 1.544 MHz
ASYNCHRONOUS OPERATION
For asynchronous operation, separate encode and decode
clocks may be applied. MCLK
E
and MCLK
D
must be
1.536 MHz or 1.544 MHz for the TP5510, and need not be
synchronous. For best transmission performance, however,
MCLK
D
should be synchronous with MCLK
E
, which is easily
achieved by applying only static logic levels to the MCLK
D
/
PDN pin. This will automatically connect MCLK
E
to all inter-
nal MCLK
D
functions (see Pin Description). For 1.544 MHz
operation, the device automatically compensates for the
193rd clock pulse each frame. FS
E
starts each A/D conver-
sion cycle and must be synchronous with MCLK
E
and
BCLK
E
. FS
D
starts each D/A conversion cycle and must be
synchronous with BCLK
D
. BCLK
D
must be a clock, the logic
levels shown in Table 1 are not valid in asynchronous mode.
BCLK
E
and BCLK
D
may operate from 64 kHz to 2.048 MHz.
SHORT FRAME SYNC OPERATION
The AFE can utilize either a short frame sync pulse or a long
frame sync pulse. Upon power initialization, the device as-
sumes a short frame mode. In this mode, both frame sync
pulses, FS
E
and FS
D
, must be one bit clock period long,
with timing relationships specified inFigure 2. With FS
E
high
during a falling edge of BCLK
E
, the next rising edge of
BCLK
E
enables the D
E
TRI-STATE output buffer, which will
output the sign bit. The following seven rising edges clock
out the remaining seven bits, and the next falling edge dis-
ables the D
E
output. With FS
D
high during a falling edge of
BCLK
D
(BCLK
E
in synchronous mode), the next falling edge
of BCLK
E
latches in the sign bit. The following seven falling
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