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參數(shù)資料
| 型號： | TP5510N |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Full Duplex Analog Front End for Consumer Applications |
| 中文描述： | 全雙工模擬前端的消費應(yīng)用 |
| 文件頁數(shù)： | 2/12頁 |
| 文件大?。?/td> | 197K |
| 代理商： | TP5510N |
Block Diagram
TL/H/11186–2
FIGURE 1
Pin Description
Symbol
Function
V
BB
Negative power supply pin. V
BB
e b
5V
g
5%.
Analog ground. All signals are referenced
to this pin.
GNDA
VF
D
O
Analog output of the receive power ampli-
fier.
Positive power supply pin. V
CC
e a
5V
g
5%.
V
CC
Symbol
Function
FS
D
Decode frame sync pulse which enables
BCLK
R
to shift data into D
D
. FS
D
is an
8 kHz pulse train. See Figures 2 and 3 for
timing details.
D
D
Decode data input. Data is shifted into D
D
following the FS
D
leading edge.
BCLK
D
/CLKSEL The bit clock which shifts data into D
D
af-
ter the FS
D
leading edge. May vary from
64 kHz to 2.048 MHz. Alternatively, may
be a logic input which selects either
1.536 MHz/1.544 MHz or 2.048 MHz for
master clock in synchronous mode and
BCLK
D
is used for both encode and de-
code directions (see Table 1).
http://www.national.com
2
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