參數(shù)資料
型號: TP3410
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 通信及網絡
英文描述: TP3410 ISDN Basic Access Echo-Cancelling 2B1Q U Transceiver
中文描述: SPECIALTY TELECOM CIRCUIT, PDIP24
文件頁數(shù): 5/32頁
文件大小: 436K
代理商: TP3410
Functional Description
1.1 Power-On Initialization
When power is first applied, power-on reset circuitry initializ-
es the TP3410 and puts it into the power-down state, in
which all the internal circuits including the Master oscillator
are inactive and in a low power state except for the Line-
Signal Detect circuit; the line outputs Lo
a
/Lo
b
are in a
high impedance state. All programmable registers and the
Activation Sequence Controller are reset.
All states in the Command Registers initialize as shown in
their respective code tables. The desired modes for all pro-
grammable functions may be selected by writing to these
registers via the control channel (Microwire or Monitor chan-
nel, as appropriate). Microwire is functional regardless of
whether the device is powered up or down, whereas the
GCI channel requires the BCLK to be running.
1.2 Power-Up/Power-Down Control
Before powering up the device, the Configuration Registers
should be programmed with the required modes.
In Microwire mode and GCI Slave mode, the device is pow-
ered up and the MCLK started by writing the PUP command,
as described in the Activation section. In GCI Master mode,
there are 2 methods of powering up the device: the Bx data
input can be pulled low (local power-up command) or the
10 kHz wake-up tone may be received from the far-end.
The power-down state may be re-entered by writing a Pow-
er-down command. In the power-down state, all pro-
grammed register data is retained. Also, if the loop had
been successfully activated and deactivated, the adaptive
circuits are ‘‘frozen’’ and the coefficients in the Digital Signal
Processors are stored to enable rapid reactivation (‘‘warm-
start’’).
1.3 Reset
A software reset command is provided to enable the clear-
ing of the Activation sequencer without disconnecting the
power supply to the device, see the Activation section.
2.0 TRANSMISSION SECTION
2.1 Line Coding And Frame Format
For both directions of transmission, 2B1Q coding is used, as
illustrated in Figure 1. This coding rule requires that binary
data bits are grouped in pairs, and each pair is transmitted
as a symbol, the magnitude of which may be 1 out of 4
equally spaced voltage levels (a ‘‘Quat’’). There is no sym-
bol value at 0V in this code, the relative quat magnitudes
being
g
1 (the ‘‘inner’’ levels) and
g
3 (the ‘‘outer’’ levels).
No redundacy is included in this code, and in the limit there
is no bound to the RDS, although scrambling controls the
RDS in a practical sense ( RDS is the Running Digital Sum,
which is the algebraic summation of all symbol values in a
transmission session).
The frame format used in the TP3410 follows the ANSI
standard, shown in Table I. Each complete frame consists
of 120 quats, with a line bit rate of 80 kq/s, giving a frame
duration of 1.5 ms. A 9 quat syncword defines the framing
boundary. Furthermore, a ‘‘superframe’’ consisting of 8
frames is defined in order to provide sub-channels within the
spare bits M1 to M6. Inversion of the syncword defines the
superframe boundary. Prior to transmission, all data, with
the exception of the syncword, is scrambled using a self-
synchronizing scrambler to implement the specified 23rd-or-
der polynomial. Descrambling is included in the receiver.
First Bit
(Sign)
Second Bit
(Magnitude)
Quat
Pulse Amplitude
(Note 1)
1
1
0
0
0
1
1
0
a
3
a
1
b
1
b
3
a
2.5V
a
0.83V
b
0.83V
b
2.5V
Note 1:
For isolated pulses into a 135
X
termination with recommended
transformer interface.
TL/H/9151–25
FIGURE 1. 2B1Q Line-Coding Rule
5
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