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TMS320TCI6482
Communications Infrastructure Digital Signal Processor
SPRS246F–APRIL 2005–REVISED MAY 2007
Table 8-112. RapidIO Control Registers (continued)
HEX ADDRESS RANGE
02D0 07EC
02D0 07F0 - 02D0 07FC
02D0 0800
02D0 0804
02D0 0808
02D0 080C
02D0 0810
02D0 0814
02D0 0818
02D0 081C
02D0 0820
02D0 0824
02D0 0828
02D0 082C
02D0 0830
02D0 0834
02D0 0838
02D0 083C
02D0 0840
02D0 0844
02D0 0848
02D0 084C
02D0 0850
02D0 0854
02D0 0858
02D0 085C
02D0 0860
02D0 0864
02D0 0868
02D0 086C
02D0 0870
02D0 0874
02D0 0878
02D0 087C
02D0 0880
02D0 0884
02D0 0888
02D0 088C
02D0 0890
02D0 0894
02D0 0898
02D0 089C
02D0 08A0
02D0 08A4
02D0 08A8
02D0 08AC
02D0 08B0
ACRONYM
REGISTER NAME
RIO_TX_QUEUE_CNTL3
-
RIO_RXU_MAP_L0
RIO_RXU_MAP_H0
RIO_RXU_MAP_L1
RIO_RXU_MAP_H1
RIO_RXU_MAP_L2
RIO_RXU_MAP_H2
RIO_RXU_MAP_L3
RIO_RXU_MAP_H3
RIO_RXU_MAP_L4
RIO_RXU_MAP_H4
RIO_RXU_MAP_L5
RIO_RXU_MAP_H5
RIO_RXU_MAP_L6
RIO_RXU_MAP_H6
RIO_RXU_MAP_L7
RIO_RXU_MAP_H7
RIO_RXU_MAP_L8
RIO_RXU_MAP_H8
RIO_RXU_MAP_L9
RIO_RXU_MAP_H9
RIO_RXU_MAP_L10
RIO_RXU_MAP_H10
RIO_RXU_MAP_L11
RIO_RXU_MAP_H11
RIO_RXU_MAP_L12
RIO_RXU_MAP_H12
RIO_RXU_MAP_L13
RIO_RXU_MAP_H13
RIO_RXU_MAP_L14
RIO_RXU_MAP_H14
RIO_RXU_MAP_L15
RIO_RXU_MAP_H15
RIO_RXU_MAP_L16
RIO_RXU_MAP_H16
RIO_RXU_MAP_L17
RIO_RXU_MAP_H17
RIO_RXU_MAP_L18
RIO_RXU_MAP_H18
RIO_RXU_MAP_L19
RIO_RXU_MAP_H19
RIO_RXU_MAP_L20
RIO_RXU_MAP_H20
RIO_RXU_MAP_L21
RIO_RXU_MAP_H21
RIO_RXU_MAP_L22
Transmit CPPI Weighted Round Robin Control Register 3
Reserved
Mailbox-to-Queue Mapping Register L0
Mailbox-to-Queue Mapping Register H0
Mailbox-to-Queue Mapping Register L1
Mailbox-to-Queue Mapping Register H1
Mailbox-to-Queue Mapping Register L2
Mailbox-to-Queue Mapping Register H2
Mailbox-to-Queue Mapping Register L3
Mailbox-to-Queue Mapping Register H3
Mailbox-to-Queue Mapping Register L4
Mailbox-to-Queue Mapping Register H4
Mailbox-to-Queue Mapping Register L5
Mailbox-to-Queue Mapping Register H5
Mailbox-to-Queue Mapping Register L6
Mailbox-to-Queue Mapping Register H6
Mailbox-to-Queue Mapping Register L7
Mailbox-to-Queue Mapping Register H7
Mailbox-to-Queue Mapping Register L8
Mailbox-to-Queue Mapping Register H8
Mailbox-to-Queue Mapping Register L9
Mailbox-to-Queue Mapping Register H9
Mailbox-to-Queue Mapping Register L10
Mailbox-to-Queue Mapping Register H10
Mailbox-to-Queue Mapping Register L11
Mailbox-to-Queue Mapping Register H11
Mailbox-to-Queue Mapping Register L12
Mailbox-to-Queue Mapping Register H12
Mailbox-to-Queue Mapping Register L13
Mailbox-to-Queue Mapping Register H13
Mailbox-to-Queue Mapping Register L14
Mailbox-to-Queue Mapping Register H14
Mailbox-to-Queue Mapping Register L15
Mailbox-to-Queue Mapping Register H15
Mailbox-to-Queue Mapping Register L16
Mailbox-to-Queue Mapping Register H16
Mailbox-to-Queue Mapping Register L17
Mailbox-to-Queue Mapping Register H17
Mailbox-to-Queue Mapping Register L18
Mailbox-to-Queue Mapping Register H18
Mailbox-to-Queue Mapping Register L19
Mailbox-to-Queue Mapping Register H19
Mailbox-to-Queue Mapping Register L20
Mailbox-to-Queue Mapping Register H20
Mailbox-to-Queue Mapping Register L21
Mailbox-to-Queue Mapping Register H21
Mailbox-to-Queue Mapping Register L22
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C64x+ Peripheral Information and Electrical Specifications
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