參數(shù)資料
型號(hào)： TMS320LF2407PZS
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號(hào)處理
英文描述： DSP CONTROLLERS
中文描述： DSP控制器
文件頁數(shù)： 53/115頁
文件大?。?/td> 1511K
代理商： TMS320LF2407PZS
SPRS094I APRIL 1999 REVISED SEPTEMBER 2003
53
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
description of shared I/O pins (continued)
Table 12. Shared Pin Configurations
(Continued)
PIN FUNCTION SELECTED
MUX
CONTROL
REGISTER
(name.bit #)
MUX CONTROL
VALUE AT RESET
(MCRx.n)
I/O PORT DATA AND DIRECTION
(MCRx.n = 1)
Primary Function
(MCRX.N = 0)
I/O
REGISTER
DATA BIT NO.§
DIR BIT NO.
PORT E
CLKOUT
IOPE0
MCRC.0
1
PEDATDIR
0
8
PWM7
IOPE1
MCRC.1
0
PEDATDIR
1
9
PWM8
IOPE2
MCRC.2
0
PEDATDIR
2
10
PWM9
IOPE3
MCRC.3
0
PEDATDIR
3
11
PWM10
IOPE4
MCRC.4
0
PEDATDIR
4
12
PWM11
IOPE5
MCRC.5
0
PEDATDIR
5
13
PWM12
IOPE6
MCRC.6
0
PEDATDIR
6
14
CAP4/QEP3
IOPE7
MCRC.7
0
PEDATDIR
7
15
PORT F
CAP5/QEP4
IOPF0
MCRC.8
0
PFDATDIR
0
8
CAP6
IOPF1
MCRC.9
0
PFDATDIR
1
9
T3PWM/T3CMP
IOPF2
MCRC.10
0
PFDATDIR
2
10
T4PWM/T4CMP
IOPF3
MCRC.11
0
PFDATDIR
3
11
TDIRB
IOPF4
MCRC.12
0
PFDATDIR
4
12
TCLKINB
IOPF5
MCRC.13
0
PFDATDIR
5
13
Reserved
IOPF6
MCRC.14
—
—
—
—
Reserved
Reserved
MCRC.15
—
—
—
—
Bold, italicized pin names indicate pin functions at reset.
Valid only if the I/O function is selected on the pin
§If the GPIO pin is configured as an output, these bits can be written to. If the pin is configured as an input, these bits are read from.
If the DIR bit is 0, the GPIO pin functions as an input. For a value of 1, the pin is configured as an output.
#At reset, all LF240x devices come up with the W/R/IOPC0 pin in W/R mode. On devices that lack an external memory interface (e.g., LF2406
and LF2402), W/R mode is not functional and MCRB.0 must be set to a 0 if the IOPC0 pin is to be used.
||Note that bits 15 through 9 of the MCRB register
must
be written as 1 only. Writing a 0 to any of these bits will cause unpredictable operation
of the device.
digital I/O control registers
Table 13 lists the registers available in the digital I/O module. As with other 240x peripherals, these registers
are memory-mapped to the data space.
Table 13. Addresses of Digital I/O Control Registers
ADDRESS
REGISTER
NAME
7090h
MCRA
I/O mux control register A
7092h
MCRB
I/O mux control register B
7094h
MCRC
I/O mux control register C
7095h
PEDATDIR
I/O port E data and direction register
7096h
PFDATDIR
I/O port F data and direction register
7098h
PADATDIR
I/O port A data and direction register
709Ah
PBDATDIR
I/O port B data and direction register
709Ch
PCDATDIR
I/O port C data and direction register
709Eh
PDDATDIR
I/O port D data and direction register
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