
SPRS094I APRIL 1999 REVISED SEPTEMBER 2003
39
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
enhanced analog-to-digital converter (ADC) module
A simplified functional block diagram of the ADC module is shown in Figure 7. The ADC module consists of a
10-bit ADC with a built-in sample-and-hold (S/H) circuit. Functions of the ADC module include:
10-bit ADC core with built-in S/H
Fast conversion time (S/H + Conversion) of 500 ns
16-channel, muxed inputs
Autosequencing capability provides up to 16 “autoconversions” in a single session. Each conversion can
be programmed to select any 1 of 16 input channels
Sequencer can be operated as two independent 8-state sequencers or as one large 16-state sequencer
(i.e., two cascaded 8-state sequencers)
Sixteen result registers (individually addressable) to store conversion values
The digital value of the input analog voltage is derived by:
Digital Value
1023
Input Analog Voltage
V
REFHI
V
REFLO
V
REFLO
Multiple triggers as sources for the start-of-conversion (SOC) sequence
S/W software immediate start
EVA Event manager A (multiple event sources within EVA)
EVB Event manager B (multiple event sources within EVB)
Ext External pin (ADCSOC)
Flexible interrupt control allows interrupt request on every end-of-sequence (EOS) or every other EOS
Sequencer can operate in “start/stop” mode, allowing multiple “time-sequenced triggers” to synchronize
conversions
EVA and EVB triggers can operate independently in dual-sequencer mode
Sample-and-hold (S/H) acquisition time window has separate prescale control
ADC calibration
Note: Refer to the following erratas for restrictions pertaining to the ADC calibration feature:
TMS320LF2402 DSP Controller Silicon Errata
(literature number SPRZ157)
TMS320LF2406 DSP Controller Silicon Errata
(literature number SPRZ159)
TMS320LF2407 DSP Controller Silicon Errata
(literature number SPRZ158)
Self-test