參數(shù)資料
型號： TMS320LF2407PZS
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： DSP CONTROLLERS
中文描述： DSP控制器
文件頁數(shù)： 33/115頁
文件大小： 1511K
代理商： TMS320LF2407PZS
SPRS094I APRIL 1999 REVISED SEPTEMBER 2003
33
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
internal memory
The TMS320LF240x devices are configured with the following memory modules:
Dual-access random-access memory (DARAM)
Single-access random-access memory (SARAM)
Flash
Boot ROM
dual-access RAM (DARAM)
There are 544 words
×
16 bits of DARAM on the 240x devices. The 240x DARAM allows writes to and reads
from the RAM in the same cycle. The DARAM is configured in three blocks: block 0 (B0), block 1 (B1), and
block 2 (B2). Block 1 contains 256 words and Block 2 contains 32 words, and both blocks are located only in
data memory space. Block 0 contains 256 words, and can be configured to reside in either data or program
memory space. The SETC CNF (configure B0 as program memory) and CLRC CNF (configure B0 as data
memory) instructions allow dynamic configuration of the memory maps through software.
When using on-chip RAM, the 240x runs at full speed with no wait states. The ability of the DARAM to allow
two accesses to be performed in one cycle, coupled with the parallel nature of the 240x architecture, enables
the device to perform three concurrent memory accesses in any given machine cycle. Externally, the READY
line or on-chip software wait-state generator can be used to interface the 2407 to slower, less expensive external
memory.
single-access RAM (SARAM)
There are 2K words
×
16 bits of SARAM on some of the 240x devices.
The PON and DON bits select SARAM
(2K) mapping in program space, data space, or both. See Table 19 for details on the SCSR2 register and the
PON and DON bits. At reset, these bits are 11, and the on-chip SARAM is mapped in both the program and data
spaces. The SARAM (starting at 8000h in program memory) is accessible in external memory space (for 2407
only), if the on-chip SARAM is not enabled.
Flash EEPROM
Flash EEPROM provides an attractive alternative to masked program ROM. Like ROM, Flash is nonvolatile.
However, it has the advantage of “in-target” reprogrammability. The LF2407 incorporates one 32K
Flash EEPROM module in program space. The Flash module has multiple sectors that can be individually
protected while erasing or programming. The sector size is non-uniform and partitioned as 4K/12K/12K/4K
sectors.
16-bit
Unlike most discrete Flash memory, the LF240x Flash does not require a dedicated state machine, because
the algorithms for programming and erasing the Flash are executed by the DSP core. This enables several
advantages, including: reduced chip size and sophisticated, adaptive algorithms. For production programming,
the IEEE Standard 1149.1
(JTAG) scan port provides easy access to the on-chip RAM for downloading the
algorithms and Flash code. This Flash requires 5 V for programming (at V
CCP
pin only) the array. The Flash runs
at zero wait state while the device is powered at 3.3 V.
See Table 1 for device-specific features.
IEEE Standard 1149.11990, IEEE Standard Test Access Port.
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