參數(shù)資料
型號: TMS320LF2407PZA
廠商: Texas Instruments, Inc.
元件分類: 數(shù)字信號處理
英文描述: DSP CONTROLLERS
中文描述: DSP控制器
文件頁數(shù): 75/115頁
文件大小: 1511K
代理商: TMS320LF2407PZA
SPRS094I APRIL 1999 REVISED SEPTEMBER 2003
75
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
TIMING EVENT MANAGER INTERFACE
PWM timings
PWM refers to all PWM outputs on EVA and EVB.
switching characteristics over recommended operating conditions for PWM timing
[H = 0.5t
c(CO)
] (see Figure 29)
PARAMETER
MIN
MAX
UNIT
tw(PWM)
td(PWM)CO
PWM outputs may be 100%, 0%, or increments of tc(CO) with respect to the PWM period.
Pulse duration, PWMx output high/low
2H+5
ns
Delay time, CLKOUT low to PWMx output switching
15
ns
timing requirements
[H = 0.5t
c(CO)
] (see Figure 30)
MIN
MAX
UNIT
tw(TMRDIR)
tw(TMRCLK)
twh(TMRCLK)
tc(TMRCLK)
Parameter TMRDIR is equal to the pin TDIRx, and parameter TMRCLK is equal to the pin TCLKINx.
Pulse duration, TMRDIR low/high
4H+5
ns
Pulse duration, TMRCLK low as a percentage of TMRCLK cycle time
40
60
%
Pulse duration, TMRCLK high as a percentage of TMRCLK cycle time
40
60
%
Cycle time, TMRCLK
4
tc(CO)
ns
tw(PWM)
td(PWM)CO
PWMx
CLKOUT
Figure 29. PWM Output Timing
CLKOUT
tw(TMRDIR)
TMRDIR
Parameter TMRDIR is equal to the pin TDIRx.
Figure 30. TMRDIR Timing
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