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參數(shù)資料
| 型號： | TMS320LF2407PZA |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | DSP CONTROLLERS |
| 中文描述： | DSP控制器 |
| 文件頁數(shù)： | 12/115頁 |
| 文件大?。?/td> | 1511K |
| 代理商： | TMS320LF2407PZA |
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SPRS094I APRIL 1999 REVISED SEPTEMBER 2003
12
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
pin functions (continued)
Table 2. LF240x Pin List and Package Options
(Continued)
PIN NAME
LF2407
LF2406
LF2402
DESCRIPTION
EXTERNAL INTERRUPTS, CLOCK
RS
133
93
28
Device reset. RS causes the 240x to terminate execution and sets PC = 0.
When RS is brought to a high level, execution begins at location zero of
program memory. RS affects (or sets to zero) various registers and status bits.
When the watchdog timer overflows, it initiates a system reset pulse that is
reflected on the RS pin.
(
↑
)
PDPINTA
7
6
36
Power drive protection interrupt input. This interrupt, when activated, puts the
PWM output pins (EVA) in the high-impedance state should motor drive/power
converter abnormalities, such as overvoltage or overcurrent, etc., arise.
PDPINTA is a falling-edge-sensitive interrupt.
(
↑
)
XINT1/
IOPA2
23
16
External user interrupt 1 or GPIO. Both XINT1 and XINT2 are edge-sensitive.
The edge polarity is programmable.
(
↑
)
XINT2/ADCSOC/
IOPD0
21
15
42
External user interrupt 2 and ADC start of conversion or GPIO. External
“start-of-conversion” input for ADC/GPIO. Both XINT1 and XINT2 are
edge-sensitive. The edge polarity is programmable.
(
↑
)
CLKOUT
/IOPE0
73
51
1
Clock output or GPIO. This pin outputs either the CPU clock (CLKOUT) or the
watchdog clock (WDCLK). The selection is made by the CLKSRC bit (bit 14)
of the System Control and Status Register (SCSR). This pin can be used as
a GPIO if not used as a clock output pin.
(
↑
)
PDPINTB
137
95
Power drive protection interrupt input. This interrupt, when activated, puts the
PWM output pins (EVB) in the high-impedance state should motor drive/power
converter abnormalities, such as overvoltage or overcurrent, etc., arise.
PDPINTB is a falling-edge-sensitive interrupt.
(
↑
)
OSCILLATOR, PLL, FLASH, BOOT, AND MISCELLANEOUS
XTAL1/CLKIN
123
87
24
PLL oscillator input pin. Crystal input to PLL/clock source input to PLL.
XTAL1/CLKIN is tied to one side of a reference crystal.
XTAL2
124
88
25
Crystal output. PLL oscillator output pin. XTAL2 is tied to one side of a
reference crystal. This pin goes in the high-impedance state when EMU1/OFF
is active low.
PLLVCCA
IOPF6
12
10
39
PLL supply (3.3 V)
131
92
General-purpose I/O
(
↑
)
BOOT_EN /
XF
BOOT_EN
121
86
23
Boot ROM enable, GPO, XF. This pin will be sampled as input (BOOT_EN) to
update SCSR2.3 (BOOT_EN bit) during reset and then driven as an output
signal for XF. After reset, XF is driven high. The BOOT_EN pin must be driven
with a passive circuit only.
(
↑
)
XF
121
86
23
Bold, italicized pin names
indicate pin function after reset.
GPIO General-purpose input/output pin. All GPIOs come up as input after reset.
§It is highly recommended that VCCA be isolated from the digital supply voltage (and VSSA from digital ground) to maintain the specified accuracy
and improve the noise immunity of the ADC.
Only when all of the following conditions are met: EMU1/OFF is low, TRST is low, and EMU0 is high
#No power supply pin (VDD, VDDO, VSS, or VSSO) should be left unconnected. All power supply pins must be connected appropriately for proper
device operation.
LEGEND:
↑
Internal pullup
↓
Internal pulldown
(Typical active pullup/pulldown value is
±
16
μ
A.)
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