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參數(shù)資料
| 型號： | TMS320LF2407PZA |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | DSP CONTROLLERS |
| 中文描述： | DSP控制器 |
| 文件頁數(shù)： | 14/115頁 |
| 文件大小： | 1511K |
| 代理商： | TMS320LF2407PZA |
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SPRS094I APRIL 1999 REVISED SEPTEMBER 2003
14
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
pin functions (continued)
Table 2. LF240x Pin List and Package Options
(Continued)
PIN NAME
LF2407
LF2406
LF2402
DESCRIPTION
EMULATION AND TEST (CONTINUED)
TRST
1
1
33
JTAG test reset with internal pulldown. TRST, when driven high,
gives the scan system control of the operations of the device. If this
signal is not connected or driven low, the device operates in its
functional mode, and the test reset signals are ignored.
(
↓
)
NOTE: Do not use pullup resistors on TRST; it has an internal
pulldown device. In a low-noise environment, TRST can be left
floating. In a high-noise environment, an additional pulldown
resistor may be needed. The value of this resistor should be based
on drive strength of the debugger pods applicable to the design. A
2.2-k
resistor generally offers adequate protection. Since this is
application-specific, it is recommended that each target board is
validated for proper operation of the debugger and the application.
ADDRESS, DATA, AND MEMORY CONTROL SIGNALS
DS
87
Data space strobe. IS, DS, and PS are always high unless low-level
asserted for access to the relevant external memory space or I/O.
They are placed in the high-impedance state.
IS
82
I/O space strobe. IS, DS, and PS are always high unless low-level
asserted for access to the relevant external memory space or I/O.
They are placed in the high-impedance state.
PS
84
Program space strobe. IS, DS, and PS are always high unless
low-level asserted for access to the relevant external memory
space or I/O. They are placed in the high-impedance state.
R/W
92
Read/write qualifier signal. R/W indicates transfer direction during
communication to an external device. It is normally in read mode
(high), unless low level is asserted for performing a write operation.
It is placed in the high-impedance state.
W/R
/ IOPC0
W/R
19
Write/Read qualifier or GPIO. This is an inverted R/W signal useful
for zero-wait-state memory interface. It is normally low, unless a
memory write operation is performed.
See Table 12, Port C
section, for reset note regarding LF2406 and LF2402.
Read-enable strobe. Read-select indicates an active, external read
cycle. RD is active on all external program, data, and I/O reads. RD
goes into the high-impedance state.
IOPC0
19
14
(
↑
)
RD
93
WE
89
Write-enable strobe. The falling edge of WE indicates that the
device is driving the external data bus (D15D0). WE is active on
all external program, data, and I/O writes. WE goes in the
high-impedance state.
STRB
96
External memory access strobe. STRB is always high unless
asserted low to indicate an external bus cycle. STRB is active for
all off-chip accesses. It is placed in the high-impedance state.
Bold, italicized pin names
indicate pin function after reset.
GPIO General-purpose input/output pin. All GPIOs come up as input after reset.
§It is highly recommended that VCCA be isolated from the digital supply voltage (and VSSA from digital ground) to maintain the specified accuracy
and improve the noise immunity of the ADC.
Only when all of the following conditions are met: EMU1/OFF is low, TRST is low, and EMU0 is high
#No power supply pin (VDD, VDDO, VSS, or VSSO) should be left unconnected. All power supply pins must be connected appropriately for proper
device operation.
LEGEND:
↑
Internal pullup
↓
Internal pulldown
(Typical active pullup/pulldown value is
±
16
μ
A.)
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