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參數(shù)資料
| 型號(hào)： | TMS320LF2407PZA |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | DSP CONTROLLERS |
| 中文描述： | DSP控制器 |
| 文件頁(yè)數(shù)： | 48/115頁(yè) |
| 文件大?。?/td> | 1511K |
| 代理商： | TMS320LF2407PZA |
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SPRS094I APRIL 1999 REVISED SEPTEMBER 2003
48
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
PLL-based clock module
The 240x has an on-chip, PLL-based clock module. This module provides all the necessary clocking signals
for the device, as well as control for low-power mode entry. The PLL has a 3-bit ratio control to select different
CPU clock rates. See Figure 11 for the PLL Clock Module Block Diagram, Table 9 for clock rates, and Table 10
for the loop filter component values.
The PLL-based clock module provides two modes of operation:
Crystal-operation
This mode allows the use of an external crystal/resonator to provide the time base to the device.
External clock source operation
This mode allows the internal oscillator to be bypassed. The device clocks are generated from an external
clock source input on the XTAL1/CLKIN pin. In this case, an external oscillator clock is connected to the
XTAL1/CLKIN pin.
XTAL2
XTAL1/CLKIN
PLL
XTAL
OSC
CLKOUT
Fin
3-bit
PLL Select
(SCSR1.[11:9])
R1
C1
C2
PLLF
RESONATOR/
CRYSTAL
PLLF2
Cb1
Cb2
Figure 11. PLL Clock Module Block Diagram
Table 9. PLL Clock Selection Through Bits (119) in SCSR1 Register
CLK PS2
CLK PS1
CLK PS0
CLKOUT
4
×
Fin
2
×
Fin
1.33
×
Fin
1
×
Fin
0.8
×
Fin
0.66
×
Fin
0.57
×
Fin
0.5
×
Fin
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Default multiplication factor after reset is (1,1,1), i.e., 0.5
×
Fin.
CAUTION:
The bootloader sets the PLL to x4 option. If the bootloader is used, the value of CLKIN used
should not force CLKOUT to exceed the maximum rated device speed. See the “Boot ROM”
section for more details.
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