參數(shù)資料
型號: TMS320LC2402APG
廠商: Texas Instruments, Inc.
英文描述: Foot Grounder; Features:1 megohm resistor; elastic strap for comfort; elastic velcro; D-ring adjustability; 3 layer sole for durability; 18" conductive ribbon RoHS Compliant: NA
中文描述: DSP控制器
文件頁數(shù): 61/133頁
文件大小: 1672K
代理商: TMS320LC2402APG
SPRS145J JULY 2000 REVISED NOVEMBER 2004
61
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
digital I/O and shared pin functions (continued)
Output Control Registers — used to control the multiplexer selection that chooses between the primary
function of a pin or the general-purpose I/O function.
Data and Control Registers — used to control the data and data direction of bidirectional I/O pins.
description of shared I/O pins
The control structure for shared I/O pins is shown in Figure 18, where each pin has three bits that define its
operation:
MUX control bit — this bit selects between the primary function (1) and I/O function (0) of the pin.
I/O direction bit — if the I/O function is selected for the pin (MUX control bit is set to 0), this bit determines
whether the pin is an input (0) or an output (1).
I/O data bit — if the I/O function is selected for the pin (MUX control bit is set to 0) and the direction selected
is an input, data is read from this bit; if the direction selected is an output, data is written to this bit.
The MUX control bit, I/O direction bit, and I/O data bit are in the I/O control registers.
Pin
(Read/Write)
IOP Data Bit
In
Out
0 = Input
1 = Output
0
1
MUX Control Bit
0 = I/O Function
1 = Primary Function
IOP DIR Bit
Primary
Function
or I/O Pin
Pullup
or
Pulldown
(Internal)
Primary
Function
(Output Section)
Primary
Function
(Input Section)
Figure 18. Shared Pin Configuration
A summary of shared pin configurations and associated bits is shown in Table 12.
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